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Approved for public release; distribution is unlimited / A pipeline technique by Loomis and Sinha has been applied to the design of recursive digital filters. Recursive digital filters operating at hitherto impossibly high rates can be designed by this technique. An alternate technique by R. Gnanasekaran allows high speed implementation using the state-space structure directly. High throughput is also achieved by use of pipelined multiply-add modules. The actual hardware complexity will depend upon the number of pipeline stages. These techniques are used for the design of the I IR notch filter and finally, a comparison of the performance and complexity of these two techniques is presented. / http://archive.org/details/infiniteimpulser00jang / Lieutenant, Royal Thai Navy

La tendance dans la conception de cartes électroniques imprimées est de remplacer les traditionnels bus parallèles par des liens série rapides dont le débit peut atteindre plusieurs dizaines de Gigabit par seconde (Gbps). Cette thèse proposée par THALES Communications & Security en collaboration avec le laboratoire SATIE de l'ENS de Cachan a pour objectif de définir une approche adaptée au traitement des problèmes de liens multi-gigahertz, de manière à garantir le fonctionnement d’une carte numérique complexe (multicouches, haute densité d'intégration, ...) sans qu’une phase de prototypage ne soit nécessaire. Après un état de l’art, ce travail s’est organisé en trois parties : La première partie porte sur l'étude du canal de propagation. La décomposition spectrale des liens multi-gigabits couvrant plusieurs gigahertz voir plusieurs dizaines de gigahertz montre la nécessité d'employer des logiciels de simulations spécifiques au domaine des hyperfréquences. Une évaluation de certains solveurs électromagnétiques 3D parmi les plus récents a été réalisée afin d'extraire les paramètres S du canal de propagation de façon précise et rapide a partir des informations issues des logiciels de CAO utilisés à THALES. La seconde partie traite de la prise en compte des émetteurs, des récepteurs et des traitements numériques associés dans la simulation afin de réaliser des calculs de diagrammes de l'œil, de taux d’erreurs binaires (BER) et de jitter. L’utilisation de la norme IBIS-AMI, très récente, et la comparaison des performances aves d’autres outils, tel que HSPICE, a demandé l'évaluation de simulateurs circuit de dernière génération. Cette étape a été réalisée en étroite collaboration avec les éditeurs des logiciels car certains outils ne sont pas suffisamment matures pour s'inscrire dans un flot global de conception. Enfin, la chaîne de simulation complète ayant été validée par la mesure, nous avons effectué une analyse approfondie des différentes composantes du jitter en fonction des phénomènes physiques plus ou moins destructeurs pour la qualité du signal. Cela nous a ensuite permis d’établir les règles et la méthodologie de conception, en tenant compte des marges allouées à partir des résultats de l’analyse du jitter. / The designers of Printed Circuit Board (named “board” below) tend to use more and more multi-gigabit serial links rather than traditional parallel buses. It enables to push back the density limitations and to increase embedded functionalities of the board. This thesis is the result of collaboration with THALES Communications & Security and the SATIE laboratory of ENS Cachan. The goal of the thesis was to define an approach dedicated to the study of Multi-GigaHertz (MGH) signals in order to assure that digital complex boards work without costly multiple prototype designs. After an inventory of the state of the arts, this work was conducted in three parts: The firt part relates to the study of the propagation channel. The spectral power distribution of the multi-gigabit links ranges from DC to several dozens of gigahertz, it is the reason why specific simulation softwares usually used in the hyper-frequency field have to be used A benchmark of several most recent 3D ElectroMagnetic (EM) solvers has been achieved in order to quickly and accurately extract the S Parameter matrix of the propagation channel thanks to information from CAO softwares used in THALES The second part consisted to take into account the transmitters, the receivers and the digital treatments associated in the circuit simulation in order to calculate eye diagrams, Bit Error Rate (BER) and Jitter separation. The benchmark of the latest generation of channel simulators was needed for the use of the recent norm IBIS-AMI and the comparison of the performances with other tools, such as HSPICE. This step has been led in close collaboration with the simulation software suppliers because some tools are not mature enough to fit into a global design flow. Finally, thanks to the validation of the simulation flow with measurements, a deep sudy of the different components of the jitter has been conducted depending on the physical phenomenon being more or less destructive for the quality of the transmission. This study enabled to define design rules and design methodology taking into account the margins allocated from the results of the jitter analysis.

"Escapement mechanisms hold back a stream of parts driven either by mechanical or pneumatic means for a length of time and release a single part as required to an assembly station. They are used in most automatic multi-component assembly equipment. They occupy a significant design space and have dynamic characteristics of their own. This research aimed to develop a novel high speed mechanism for parts escapement that occupies less design space and contributes less to the dynamic activity of the structure. Several conceptual mechanisms were generated and evaluated. A compliant mechanism that amplifies the very small displacement of a piezo actuator was selected for detailed design. A proof of concept prototype was fabricated and tested. A piezo stack was used to bend a thin, spring steel, compliant beam. Its deflection was further amplified by attaching a comparatively rigid beam extension at the end of the compliant section. The mechanism escapes parts at 16 Hz using constrained layer damping on the beam to reduce vibrations. The concept is feasible to use on production machinery and provides advantages in terms of higher operating speeds and compactness. The concept could also be used where there is a requirement of high speed gating."