Tato diplomová práce se zabývá návrhem IP bloku pro diskrétní kosinovou transformaci. V~teoretické části jsou shrnuty algoritmy pro výpočet diskrétní kosinové transformace a diskutována jejich použitelnost v~hardwaru. Zvolený algoritmus pro hardwarovou implementaci je modelován v jazyce C. Poté je popsán na RTL úrovni, verifikován a je provedena syntéza v~technologii TSMC 65 nm. Hardwarová implementace je poté zhodnocena s ohledem na datovou propustnost, plochu, rychlost and spotřebu.

The thesis aims to implement different digital filters such as finite impulse response (FIR), infinite impulse response (IIR) and cascade integrator comb (CIC) on the field-programmable gate array (FPGA) development board using hardware description language (VHDL). To this purpose, Intel’s systems integration tool Platform designer is used to convert the implementation to an IP core. The implemented FIR and IIR filters include different filter types such as lowpass, highpass, bandpass and bandstop. All the filters have a pipeline architecture as well as adjustable parameters such as filter order, frequency specifications and resolution. The coefficients of the filters are calculated according to the user's specifications. The calculated coefficients are verified using simulation. Furthermore the IP has been validated on hardware by the FPGA board MAX DE-10 lite. The IP is also analyzed regarding timing and power consumtion with good results. FIR filters of different types have been implemented and tested up to 501 taps with a coefficient width of 24 bits, which covered just below 50% of the available logic gates on the MAX 10-DE lite board with 50000 gates in total. The FIR filters have an option to be used with a Kaiser window with a maximum tap level of 51. Different IIR filters have also been implemented and tested on the hardware. However, the results have shown that the IIR filters do not perform so well, especially those of order higher than 6. One of the main reasons for this is the overflow caused by instability of the IIR.