This research presents design techniques for a linear power amplifier with high efficiency in wireless handsets. The power amplifier operates with high efficiency at the saturated output power, maintains high linearity with enhanced efficiency at back-off power levels, and covers a broadband frequency response. The amplifier is thus able to operate in multiple modes (2G/2.5G/3G/4G). The design techniques provide contributions to current research in handset power amplifiers, especially to the converged power amplifier architecture, to reduce the number of power amplifiers within the handset while covering all standards and frequency bands around the globe. Three main areas of interest in power amplifier design are investigated: high power efficiency; high linearity; and broadband frequency response. Multiple techniques for improving the efficiency are investigated with the focus on maintaining linear operation. The research applies a new technique to the handset industry, class-J, to improve the power efficiency while avoiding the practical issues that hinder the typical techniques (class-AB and class-F). Class-J has been implemented using GaN FET in high power applications. To our knowledge, this work provides the first implementation of class-J using GaAs HBT in a handset power amplifier. The research investigates the linearity, and the nature and causes of nonlinearities. Multiple concepts for improving the linearity are presented, such as avoiding odd-degree harmonics, and linearizing the relationship between the output current and the input voltage of the amplifier at the fundamental frequency. The concept of bias depression in HBT transistors is introduced with a bias circuit that reduces the bias-offset effect to improve linearity at high output power. A design methodology is presented for broadband matching networks, including the component loss. The methodology offers a quick and accurate estimation of component values, giving more degrees of freedom to meet the design specifications. It enables a trade-off among high out-of-band attenuation, number/size of components, and power loss within the network. Although the main focus is handset power amplifiers, most of the developed techniques can be applied to a wide range of power amplifiers. / Ph. D.

Five chapters of this dissertation concentrate on the characterization and cancellation of high frequency parasitic parameters in EMI filters. One chapter addresses the interaction between the power interconnects and the parasitic parameters in EMI filters. The last chapter addresses the characterization, evaluation and design of noise separators. Both theoretical and experimental analyses are applied to each topic. This dissertation tries to explore several important issues related to EMI filters and noise separators. The author wishes to find some helpful approaches to benefit the understanding and design of EMI filters. The contributions of the dissertation can be summarized below: 1) Identification of mutual couplings and their effects on EMI filter performance 2) Extraction of mutual couplings using scattering parameters 3) Cancellation of mutual couplings to improve EMI filter performance 4) Cancellation of equivalent series inductance to improve capacitor performance 5) Analysis of mode transformations due to the imperfectly balanced parameters in EMI filters 6) Analysis of interaction between power interconnects and EMI filters on filter high-frequency performance 7) Modeling and design of high-performance noise separator for EMI diagnosis 8) Identification of the effects of parasitics in boost PFC inductor on DM noise Although all topics are supported by both theory and experiments, there may still be some mistakes in the dissertation. The author welcomes any advice and comments. Please send them via email to shuowang@ieee.org. Thanks / Ph. D.