Information anytime and anywhere has ushered in a new technological age where massive amounts of ‘big data’ combined with self-aware and ubiquitous interactive computing systems is shaping our daily lives. As society gravitates towards a smart living environment and a sustainable future, the demand for faster and more computationally efficient electronics will continue to rise. Keeping up with this demand requires extensive innovation at the transistor level, which is at the core of all electronics. Up until recently, classical silicon transistor technology has traditionally been weary of disruptive innovation. But with the aggressive scaling trend, there has been two dramatic changes to the transistor landscape. The first was the re-introduction of metal/high-K gate stacks with strain engineering in the 45 nm technology node, which enabled further scaling on silicon to smaller nodes by alleviating the problem of gate leakage and improving the channel mobility. The second innovation was the use of non-planar 3D silicon fins as opposed to classical planar architectures for stronger electrostatic control leading to significantly lower off-state leakage and other short-channel effects. Both these innovations have prolonged the life of silicon based electronics by at least another 1-2 decades. The next generation 14 nm technology node will utilize silicon fin channels that have gate lengths of 14 nm and fin thicknesses of 7 nm. These dimensions are almost at the extreme end of current lithographic capabilities. Moreover, as fins become smaller, the parasitic capacitances and resistances increase significantly resulting in degraded performance. It is of popular consensus that the next evolutionary step in transistor technology is in the form of gate-all-around silicon nanowires (GAA NWFETs), which offer the tightest electrostatic configuration leading to the lowest possible leakage and short channel characteristics in over-the-barrier type devices. However, to keep scaling on silicon, the amount of current generated per device has to be increased while keeping short channel effects and off-state leakage at bay. The objective of this doctoral thesis is the investigation of an innovative vertical silicon based architecture called the silicon nanotube field effect transistor (Si NTFET). This topology incorporates a dual inner/outer core/shell gate stack strategy to control the volume inversion properties in a hollow silicon 1D quasi-nanotube under a tight electrostatic configuration. Together with vertically aligned source and drain, the Si NTFET is capable of very high on-state performance (drive current) in an area-efficient configuration as opposed to arrays of gate-all-around nanowires, while maintaining leakage characteristics similar to a single nanowire. Such a device architecture offsets the need of device arraying that is needed with fin and nanowire architectures. Extensive simulations are used to validate the potential benefits of Si NTFETs over GAA NWFETs on a variety of platforms such as conventional MOSFETs, tunnel FETs, junction-less FETs. This thesis demonstrates a novel CMOS compatible process flow to fabricate vertical nanotube transistors that offer a variety of advantages such as lithography-independent gate length definition, integration of epitaxially grown silicon nanotubes with spacer based gate dielectrics and abrupt in-situ doped source/drain junctions. Experimental measurement data will showcase the various materials and processing challenges in fabricating these devices. Finally, an extension of this work to topologically transformed wavy channel FinFETs is also demonstrated keeping in line with the theme of area efficient high-performance electronics.

Afin de concurrencer les mémoires à accès aléatoire de type DRAM actuellement sur le marché, les mémoires magnétiques ont depuis quelques années fait l'objet de nombreuses études afin de les rendre aussi performantes que possible. Dans ce contexte, les jonctions tunnel magnétiques à double barrière pourraient présenter des avantages significatifs en termes de vitesse de lecture et de consommation électrique. Nous avons en effet fait la démonstration que les structures à double barrière permettent, pour une configuration antiparallèle des aimantations des polariseurs, d'accroître les effets de transfert de spin assurant ainsi des courants d'écriture faibles. Dans la configuration parallèle des polariseurs, le phénomène est inversé et le couple par transfert de spin résultant est considérablement réduit. Cela permettrait de lire l'information plus rapidement en utilisant des tensions du même ordre de grandeurs que celles utilisées pour l'écriture. Nous avons par ailleurs proposé une méthode d'analyse permettant de caractériser les deux barrières tunnel par des mesures électriques en pleine plaque, ce qui facilite le développement des matériaux et atteste des propriétés électriques attendues avant nanofabrication. / Since a few years, magnetic memories have been extensively studied in order to compete with already existing Random Access Memories such as DRAM. In this context, double barrier magnetic tunnel junctions may have significant assets in terms of reading speed and electrical consumption. In fact, we demonstrated that spin transfer torque is enhanced when polarizers magnetizations are antiparallel, thus yielding a decrease of the writing current. On the contrary, when polarizers are parallel, spin transfer torque is drastically shrinked, thus allowing fast reading of the storage layer state at a voltage as large as the writing voltage. Moreover, we proposed an analysis method to characterize both tunnel barriers by full-sheet electrical measurements, leading to considerable gain of time in material developpement.