Embedded network software has become increasingly interesting for both researchand business as more and more networked embedded systems emerge.Well-known infrastructure protocol stacks are reimplemented on new emergingembedded hardware and software architectures. Also, newly designed orrevised protocols are implemented in response to new application requirements.However, implementing protocol stacks for embedded systems remains a timeconsumingand error-prone task due to the complexity and performance-criticalnature of network software. It is even more so when targeting resource constrainedembedded systems: implementations have to minimize energy consumption,memory usage and so on, while programming efficiency is needed toimprove on time-to-market, scalability, maintainability and product evolution.Therefore, it is worth researching on how to make protocol stack implementationsfor embedded systems both easier and more likely to be correct withinthe resource limits.In the work we present in this thesis, we take a language-based approachand aim to facilitate the implementation of protocol stacks while realizingperformance demands and keeping energy consumption and memory usagewithin the constraints imposed by embedded systems. Language technologyin the form of a type system, a runtime system and compiler transformationscan then be used to generate efficient implementations. We define a domainspecificembedded language (DSEL), Implementation of Protocol Stacks (IPS),for declaratively describing overlaid protocol stacks. In IPS, a high-level packetspecification is dually compiled into an internal data representation for protocollogic implementation, and packet processing methods which are thenintegrated into the dataflow framework of a protocol overlay specification.IPS then generates highly portable C code for various architectures from thissource. We present the compilation framework for generating packet processingand protocol logic code, and a preliminary evaluation of our compiled code. / IPS

The promising results of deep learning (deep neural network) models in many applications such as speech recognition and computer vision have aroused a need for their realization on embedded platforms. Augmenting DL (Deep Learning) in embedded platforms grants them the support to intelligent tasks in smart homes, mobile phones, and healthcare applications. Deep learning models rely on intensive operations between high precision values. In contrast, embedded platforms have restricted compute and energy budgets. Thus, it is challenging to realize deep learning models on embedded platforms. In this thesis, we define the objectives of implementing deep learning models on embedded platforms. The main objective is to achieve efficient implementations. The implementation should achieve high throughput, preserve low power consumption, and meet real-time requirements.The secondary objective is flexibility. It is not enough to propose an efficient hardware solution for one model. The proposed solution should be flexible to support changes in the model and the application constraints. Thus, the overarching goal of the thesis is to explore flexible methods for efficient realization of deep learning models on embedded platforms. Optimizations are applied to both the DL model and the embedded platform to increase implementation efficiency. To understand the impact of different optimizations, we chose recurrent neural networks (as a class of DL models) and compared its' implementations on embedded platforms. The comparison analyzes the optimizations applied and the corresponding performance to provide conclusions on the most fruitful and essential optimizations. We concluded that it is essential to apply an algorithmic optimization to the model to decrease it's compute and memory requirement, and it is essential to apply a memory-specific optimization to hide the overhead of memory access to achieve high efficiency. Furthermore, it has been revealed that many of the work understudy focus on implementation efficiency, and flexibility is less attempted. We have explored the design space of Convolutional neural networks (CNNs) on Epiphany manycore architecture. We adopted a pipeline implementation of CNN that relies on the on-chip memory solely to store the weights. Also, the proposed mapping supported both ALexNet and GoogleNet CNN models, varying precision for weights, and two memory sizes for Epiphany cores. We were able to achieve competitive performance with respect to emerging manycores. As a part of the work in progress, we have studied a DL-architecture co-design approach to increase the flexibility of hardware solutions. A flexible platform should support variations in the model and variations in optimizations. The optimization method should be automated to respond to the changes in the model and application constraints with minor effort. Besides, the mapping of the models on embedded platforms should be automated as well.

The requirements of safety-critical real-time embedded systems pose unique challenges on their design process which cannot be fulfilled with traditional development methods. To ensure their correct timing and functionality, it has been suggested to move the design process to a higher abstraction level, which opens the possibility to utilize automated correct-by-design development flows from a functional specification of the system down to the level of Multiprocessor Systems-on-Chip (MPSoCs). ForSyDe, an embedded system design methodology, presents a flow of this kind by basing system development on the theory of Models of Computation and side-effect-free processes, making it possible to separate the timing analysis of computation and communication of process networks. To be able to offer guarantees on the timing of tasks implemented on a MPSoc, the hardware platform needs to provide predictability and composability in every component, which in turn requires a range of special considerations in its design. This thesis presents a predictable and composable FPGA-based MPSoC template based on the Altera Nios II soft processor and Avalon Switch Fabric interconnection structure and its integration into the automated ForSyDe system design flow. To present the functionality and to test the validity of timing predictions, two sample applications have been developed and tested in the context of the design flow as well as on the implemented hardware platform.

Energismarta lösningar är väldigt aktuellt och alla möjligheter till att spara energi anses absolut nödvändiga för att värna om naturen. Energi kan sparas på bevattningsanläggningar genom att inte vattna om nederbörd är annalkande. Via övervakningar av väderleksrapporter kan nederbärdsmängden analyseras och bevattningen anpassas efter det.   Målet med detta examensarbete är att ta fram en prototyp av ett energismart bevattningssystem, avsedd att spara in på oönskad bevattning. Via fuktmätning och analys av väderdata kommer bevattningsmängden att avgöras beroende på fuktigheten i jorden samt annalkande nederbördsmängd. Via en webbsida finns konfigureringsmöjligheter samt information angående aktuellt bevattningssystem.   I rapporten förklaras vad sensornoder har för olika funktionaliteter i systemet. Den tillhörande fuktsensorns egenskaper och dess kalibrering beskrivs. Även vattenpumpen med tillhörande styrning behandlas. Bevattningssystemets server och databas beskrivs samt kopplingen dem emellan. Det finns även ett flödesschema över serverns process. Vidare förklaras hur väderdata hämtas och analyseras för att ta fram annalkande nederbördsmängd. Bevattningssystemets webbsida skildras och beskrivs med dess konfigureringsmöjligheter och informationsvisning. Även förklaringar på hur sensornoder läggs till, tas bort och konfigureras på webbsidan och i bevattningssystemet.   Resultatet sammanfattar arbetet i sin helhet med hur de olika delarna knyts samman och bildar det energismarta bevattningssystemet. Även en installationsguide samt användaranvisningar har tagits fram. / Energy smart solutions are up to date and all opportunities to save energy are considered essential for protection of nature. Energy can be saved on irrigation systems by not watering if rain is approaching. By monitoring weather forecasts, the rainfall can be analyzed and irrigation adjusted accordingly.   The projects goal is to create an energy smart irrigation system designed to prevent unwanted watering. By using soil moisture sensors and analyze weather data, the irrigation amount will be determined depending on the soil moisture and upcoming rainfall. Through a web page, there are configuration options and information about the system.   This report explains the sensor nodes and its various functionalities in the system. The associated soil moisture sensors characteristics and its calibration are described. The water pump and its associated controlling are also treated. The system’s server and database are described as well as the link between them. There is also a flowchart of the server’s functionality. It explains how the weather data is collected and analyzed to access impending rainfall.   The system's web page is shown and described with its configuration options and its status information. It also explains how the sensor motes are added, removed and edited on the website and in the system.   The results summarize the work with how the different parts are linked together to form the energy smart irrigation system. An installation guide and a user manual have also been created.

Electricity is an essential element in today’s society, and to ensure its availability, Intelligent Electronic Devices (IEDs) are installed in power grids to detect and isolate faults by running protectionfunctions. These devices run very complex configurations with strong real-time requirements, andcan reach very high CPU utilisation’s that might affect timing requirements. However, many ofthese devices are built with other specific processors in the SoC, such as DSPs. This thesis evaluates possible ways to offload the execution of certain CPU protection functions to the DSP, toimprove system efficiency and allow more complex configurations to be executed. For this purpose,two frameworks are proposed and evaluated that enable communication and synchronisation betweenheterogeneous processors to perform simultaneous execution of functions on both processors. Thefirst framework allows the extraction of the execution of individual functions, while the secondframework performs the extraction of the execution of an entire process. The proposed frameworksare evaluated over general system configurations and Hitachi Energy product-specific configurations. Both give favourable results, being the first framework more effective to reduce the CPUutilisation of the general cases and specific cases of the current product, resulting in a reductionof CPU usage up to 14%. Although the second framework would allow the development of moreoptimal systems if the system were designed with this framework into account ensuring a high DSPutilisation, allowing configurations that would be equivalent up to 111% CPU usage without the useof the frameworks.

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Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between FPGA and ASICs for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be embedded into FPGAs to efficiently compute the result of multi-operand additions. The first contribution of this work is a Design Space Exploration (DSE) of the FPCAs and the identification of trade-offs between different parameters which describe them. Methods for analyzing and pruning the design space are proposed to enable a smart exploration. Finally, a set of best performing architectures in terms of area and delay is determined. Secondly, a study of possible integration schemes to build a hybrid FPGA/FPCA chip is performed. The goal is to find a solution with optimal usage of on-chip silicon area. The advantages and disadvantages of each solution are studied and a new integration solution based on properties of FPCAs is suggested. A VLSI implementation proves the applicability of the proposed solutions.

The recent development for multimedia applications on mobile terminals raised the need for flexible and scalable computing platforms that are capable of providing considerable (application specific) computational performance within a low cost and a low energy budget. The MPSoC with multi-disciplinary approach, resolving application mapping, platform architecture and runtime management issues, provides such multiple heterogeneous, flexible processing elements. In MPSoC, the run-time manager takes the design time exploration information as an input and selects an active Pareto point based on quality requirement and available platform resources, where a Pareto point corresponds to a particular parallelization possibility of target application. To use system’s scalability at best and enhance application’s flexibility a step further, the resource management and Pareto point selection decisions need to be adjustable at run-time. This thesis work experiments run-time Pareto point switching for MPEG-4 encoder. The work involves design time exploration and then embedding of two parallelization possibilities of MPEG-4 encoder into one single component and enabling run-time switching between parallelizations, to give run-time control over adjusting performance-cost criteria and allocation de-allocation of hardware resources at run-time. The newer system has the capability to encode each video frame with different parallelization. The obtained results offer a number of operating points on Pareto curve in between the previous ones at sequence encoding level. The run-time manager can improve application performance up to 50% or can save memory bandwidth up to 15%, according to quality request.

Software product line (SPL) engineering has become common practice for mass production and customization of software. A software product line comprises a family of software systems which share a managed core set of artifacts. There are also a set of well-defined variabilities between the products of a product line. The main idea in SPL engineering is to enable systematic reuse in different phases of software development to reduce cost and time to release. Model-Based Testing (MBT) is a technique that is widely used for checking the quality of software systems. In MBT, test cases are generated from an abstract model, which captures the desired behavior of the system. Then, the test cases are executed against a real implementation of the system and the compliance of the implementation to the specification is checked by comparing the observed outputs with the ones prescribed by the model. Software product lines have been applied in many domains in which sys- tems are mission critical and MBT is one of the techniques that is widely used for quality assurance of such systems. As the number of products can be potentially large in an SPL, using conventional approaches for MBT of the products of an SPL individually and as single systems can be very costly and time consuming. Hence, several approaches have been proposed in order to enable systematic reuse in different phases of the MBT process. An efficient modeling technique is the first step towards an efficient MBT technique for SPLs. There have been several formalisms proposed for modeling SPLs. In this thesis, we conduct a study on such modeling techniques, focusing on three fundamental formalisms, namely featured transition systems, modal transition systems, and product line calculus of communicating systems. We compare the expressive power and the succinctness of these formalisms. Furthermore, we investigate adapting existing MBT methods for efficient testing of SPLs. As a part of this line of our research, we adapt the test case generation algorithm of one of the well-known black-box testing approaches, namely, Harmonized State Identification (HSI) method by exploiting the idea of delta-oriented programming. We apply the adapted test case generation algorithm to a case study taken from industry and the results show up to 50 percent reduction of time in test case generation by using the delta-oriented HSI method. In line with our research on investigating existing MBT techniques, we compare the relative efficiency and effectiveness of the test case generation algorithms of the well-known Input-Output Conformance (ioco) testing approach and the complete ioco which is another testing technique used for input output transition systems that guarantees fault coverage. The comparison is done using three case studies taken from the automotive and railway domains. The obtained results show that complete ioco is more efficient in detecting deep faults (i.e., the faults reached through longer traces) in large state spaces while ioco is more efficient in detecting shallow faults (i.e., the faults reached through shorter traces) in small state spaces.