Verification of microprocessors is a vital phase in their development. It takes majority of time and cost in the microprocessor development. Verification can be split into two; coverage and check. In coverage we try to find out if all desired conditions are executed. Where as in check, we try to find out if the behaviour of the DUT is as expected. In this thesis we concentrate more on coverage. The test bench should be able to cover all the cases, hence methodologies have to be used which will not only reduce the total time of the project but also get maximum coverage to increase the bug detection chances. Random simulation helps to quickly attain corner cases that would not have been found by the traditional directed testing. In this thesis functional verification for the microprocessor M6802 was implemented. Few verification approaches were implemented to find out their feasibility. It was found out that random generation had many advantages over directed testing but both the approaches failed to attain good coverage in reasonable time. To overcome this other implementations were explored such as coverage driven and machine learning. Machine learning showed significant improvement over the other methods for coverage on the filp side it required a lot of setup time. It was found out that the combination of these approaches have to be used to reduce the setup time and get maximum coverage. The method to be selected depends on the complexity of the processor and the functional coverpoint.

Digital coherent receivers stand today as a promising technology for the next generation of high-capacity optical systems. Coherent systems enable the use of multilevel modulation formats which increase the spectral efficiency of a system. Key challenges of multilevel coherent systems are the strict laser linewidth requirements and receiver complexity which prevent a cost-effective implementation. The goal of this thesis is to address these challenges by investigating a novel approach to implement phase noise tolerant optical systems. The performance of a phase recovery scheme, normalized Viterbi-Viterbi carrier phase estimation (V-V CPE), is investigated for circular m-level quadrature amplitude modulation (C-mQAM) signals. C-mQAM provides inherent characteristics for phase noise mitigation, while V-V CPE enables an efficient hardware implementation in a blind feed-forward receiver. A coherent C-mQAM system was simulated in VPItransmissionMaker with phase recovery implemented with MATLAB. Phase noise tolerance was analyzed for C-16QAM and C-64QAM signals. Results show an enhanced phase noise tolerance at a low sensitivity penalty. The achieved linewidth tolerance shows an enhanced performance over available CPE schemes for square mQAM signals, and enables the use of cost-effective lasers. C-mQAM signals allow a straightforward employment of V-V CPE, which can be easily upgraded for higher order circular modulations without adding significant complexity. By combining the power of normalized V-V CPE with C-mQAM inherent characteristics, the phase noise tolerance is enhanced with an efficient implementation. These results show that C-mQAM implemented with V-V CPE is a viable and promising alternative for phase noise tolerant high-speed optical coherent systems.

One of the major challenges that mobile operators are facing is the increasing power consumption costs as a consequence of the network densication experienced in current and future mobile access networks. This power increase causes both financial and environmental concerns to operators, since both the operational expenses and the CO2 emissions are affected. This Master Thesis investigates and analyses various deployment architectures in urban and suburban areas, considering both the radio access and backhaul segments, as well as system solutions that are expected to increase the energy efficiency of Long Term Evolution (LTE) networks, such as Discontinuous Transmission - Discontinuous Reception (DTX-DRX) enhancement of future mobile networks. During this dissertation, it is investigated whether power efficient solutions can also be cost efficient in terms of Total Cost of Ownership (TCO) in urban environments. Additionally, the DTXDRX enhancement of HetNets is studied on a dense urban case, providing both nancial and environmental benefits by its utilization. The main results indicate that significant power and TCO savings can be achieved by the deployment of Heterogeneous Networks in urban environments. Fiber optics backhauling seems to be more attractive compared to Microwaves in these areas. Finally, DTX-DRX enhanced HetNets result in high power savings and can be financially attractive under particular conditions.

As large uniprocessors are no longer scaling in performance, chip multiprocessors (CMP) become the mainstream to build high-performance computers. CMP chips integrate various components such as processing cores, L1 caches and L2 caches (some also contain L3 caches, for example, in the IBM Power7 multicore processor) together, and multiple CMP chips with external memory banks make up a CMP system. As buses (although long the mainstay of system interconnect) are unable to keep up with increasing performance requirements, network-on-chip (NoC) offers an attractive solution to this communication crisis and is becoming the pervasive interconnection network in CMPs. In NoC based CMP systems, regulating traffic flows has been shown to be an effective means to improve communication performance and reduce buffer requirements. However, existing flow regulation policies such as the ones describe in [8] and [9] are all static. The parameters (δ,ρ) of the regulators are hard-coded during system configuration, where δ bounds the traffic burst and ρ the traffic rate. Although static flow regulator can be used as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communication, the drawbacks from its static property cancel the gains in some situations. In this thesis, we design a fuzzy flow regulation mechanism for network-onchip based CMPs. Being different from static flow regulation policy, our system makes regulation decisions dynamically according to the state of interconnection network. We use fuzzy logic to mimic the behaviors of an expert that validly controls the admission of input flows, with the aim of making better use of on-chip resources and decreasing communication delays. We implement and test our design under Multi-facet’s General Executiondriven Multiprocessor Simulator (GEMS), which creates a platform that is similar to real CMP environment. Hardware imitating models such as L1 caches, L2 caches and memory banks help us to test our design thoroughly and comprehensively. The experiments are done with both closed-loop and open-loop methods. Comparisons have been made between our design and static regulation policy. The results show that our fuzzy flow regulation system can make good regulation policy with all the testing cases.

This project focuses on the investigation of Silicon based Tandem solar cell fabricated by using the Hydride Vapor Phase Epitaxy (HVPE). In the state-of-the-art multi-junction solar cell manufacturing epitaxial technologies are used for sub-cell formation, such as MOVPE (Metal Organic Vapour Phase Epitaxy) [1] or MBE (Molecular Beam Epitaxy) [2]. Tandem solar cell structures consist of subcells made of III-V semiconductors serially connected or grown on a suitable semiconductor substrate [3]. The used semiconductor materials have to be lattice matched to each other and with optimum band gap combinations [4]. Multi-junction solar cells with Si and III-V semiconductor sub-cells are promising to achieve extremely high efficiency. The objective of this project is to investigate a cost effective fabrication technology to realize III-V semiconductor and silicon based sub-cells in tandem solar cells. The Si p-n junction formation by PH3 diffusion for the silicon sub cell is studied in HVPE. A prototype InP solar cell was fabricated by HVPE and its I-V performance was studied. In this thesis, the impact of HVPE process parameters on the silicon p-n junction formation was examined by alternating the process temperature. Silicon samples were processed in the HVPE with temperature values of 1st (605 0C) < 2nd (657 0C) < 3rd (720 0C). It is observed that the temperature affects the quality of the formed Si p-n junction. The Si samples treated at 720 0C show a diode performance with a deviated I-V curve due to parasitic resistances. The InP solar cell fabrication consisted of the epitaxial growth of sulfur doped n-InP and zinc doped p-InP materials on top of each other to form n+/n+/n-/p+ [5] structure. Ohmic conduction through the InP solar cell structure was observed after the contacts formation, which could be due to the metal alloy spiking through the p-InP emitter layer during annealing. Process mitigations to fabricate InP solar cell by HVPE are proposed at the end of project.

There has been extensive research in the low power Wireless Sensor Network (WSN) community with 802.15.4 based platforms. A major factor for this is the support for 802.15.4 based platforms in lightweight Operating Systems (OS) for Internet of Things (IoT) devices. Bluetooth Low Energy (BLE) with its standardized protocol and wide adoption in mobile devices is well suited to all applications requiring direct interaction with a mobile device. BLE does not have support in any of these software platforms for IoT development. With this as motivation this thesis creates a port of Contiki OS to a BLE platform, specifically a platform based on nrf51822 System on Chip (SoC). This will enable direct communication of Contiki nodes with smart-phones and ease development of BLE based projects with Contiki. This thesis extends the research on BLE by comparing its link layer with 802.15.4’s Contiki- MAC and Null-RDC on four metrics, namely data rate, latency, reliability and energy consumption. Their behavior with and without external WiFi interference also has been looked into. The tests conducted showcases the performance of simple point to point communication 802.15.4, which is rarely benchmarked in research community that prefers testing complex topologies. The effect of the limits of the number of packets communicated per connection interval in different BLE stacks can be seen on the data rate achievable with BLE. The influence of frequency hopping on the reliability of BLE communication with the presence of external interference is assessed. Adaptive Frequency Hopping (AFH) has been emulated by manually choosing interference free channel map and its effect on mitigating interference has been evaluated. Tests also assesses the impact of BLE link layer configuration, especially creating an asymmetric connection by using non zero slave latency value on latency and energy consumption. With this asymmetric connection, the slave devices have been recorded to a latency of 16 ms with Radio Duty Cycle (RDC) of 0.6%.

Semiconductor devices such as transistors and integrated circuits are everywhere in our daily lives, it's one of the most important foundations of today's information society. Nanotechnology enables the production of lighter, faster and more efficient components and systems. Manufacturing technology has improved considerably over the past 40 years, but in recent years, the bulk transistors have reaching the limits of Moore’s law as the size shrinking too few tens of nanometers. The main difficulties are to reduce the power consumption, improve the speed meanwhile maintain the low manufacturing cost. This has given an opportunity for some emerging semiconductor technologies. One of the most promising approaches is implementation of new device architectures, such as FinFET and UTBSOI. This bachelor thesis covers the basics of compact modeling of UTBSOI MOSFET, by using the BSIMSOI compact model and SPICE software Cadence to model the KTH Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) transistor. The result of this paper shows the accuracy of BSIMSOI and can be used for future extraction work. / Halvledarkomponenter såsom transistorer och integrerade kretsar finns överallt i vår vardag, det är en av de viktigaste grunderna för dagens informationssamhälle. Nanoteknik möjliggör produktion av lättare, snabbare och effektivare komponenter och system. Tillverkningstekniken har förbättrats avsevärt under de senaste 40 åren, men på de senaste åren har de bulktillverkade transistorerna nått gränserna för Moores lag, när storleken krymper till några tiotal nanometer. De största svårigheterna är att minska energiförbrukningen, förbättra hastigheten samt bevara den låga tillverkningskostnaden. Detta har gett möjlighet för att utvecklar ny halvledarteknik. En av de mest lovande metoderna är implementering av nya transitor arkitekturer, till exempel FinFET och UTBSOI. Detta examensarbete omfattar grunderna i modellering av SOIMOSFET, med hjälp av BSIMSOI och SPICE programvara Cadence kan man modellera KTH transistor. Resultatet av denna studie visar noggrannheten hos BSIMSOI och kan användas för framtida arbete inom ämnet.

Spatially-programmed architectures such as FPGA are among the most prevailing hardware in various application areas. However FPGA suffers from great overheads such as area, latency and power efficiency. Coarse-grained Reconfigurable Architecture (CGRA) is designed in order to compensate these disadvantages of FPGA. In this thesis, a Triggered Instruction based novel CGRA designed by Intel is evaluated. Benchmark work in this thesis focuses on signal processing area. Three performance limiting functions, Channel Estimation, Radix-2 FFT and Interleaving are selected from LTE Uplink Receiver PHY Benchmark which is an open source benchmark, and implemented and analyzed in Triggered Instruction Architecture (TIA). Throughput-area relationships and throughput/area-area relationships are summarized in curves using a resource estimation method. The benchmark result shows that TIA offers good flexibility for temporal and spatial execution, and a mix of them. Designs in TIA are scalable and adjustable according to different performance requirement. Moreover, based on the development work, this thesis discusses development flow of TIA, various programming techniques, low latency mapping solutions, code size comparison, development environment and integration of heterogeneous system with TIA.

Content distribution is the main driver for Internet traffic growth. The traditional networking approach, focused on communication between hosts, cannot efficiently cope with the evolving problem. Thus, information-centric networking (ICN) is a research area that has emerged to provide efficient content distribution solutions by shifting the focus from connecting hosts to connecting information. This new architecture defines named data objects as the main network entity and is based on a publish/subscribe-like paradigm combined with pervasive caching. An open challenge is a scalable routing mechanism for the vast number of objects in the global network. The Network of Information (NetInf) is an ICN architecture that pursues a scalable and efficient global routing mechanism using name resolution service, which maps the content publisher to a set of routing hints. The routing hints aid at forwarding the request towards a source of the content, based on a priority system. Topological aggregation on the publisher authority names and on the location-independent routing hints provide a scalable solution. This thesis extends the routing and forwarding scheme by forming partially ordered sets of routing hints, in order to prevent routing loops. In addition, the system has to meet the routing scalability and high performance requirements of a global solution. A dynamic routing service is investigated through an interface to open source routing software, which provides implementations of the existing routing protocols, in particular Quagga with BGP. The experimental evaluation of the forwarding scheme measures the execution times of the functions in the forwarding process by collecting timestamps. The results identify the most expensive functions and potential bottlenecks under high workload.

The rapid expansion of the internet has led to the Big Data era. Companies that provide services which deal with Big Data have to face two major issues: i) storing petabytes of data and ii) manipulating this data. On the one end the open source Hadoop ecosystem and particularly its distributed file system HDFS comes to take care of the former issue, by providing a persistent storage for unprecedented amounts of data. For the latter, there are many approaches when it comes to data analytics – from map-reduce jobs to information retrieval and data discovery. This thesis provides a novel approach to information discovery firstly by providing the means to create, manage and associate metadata to HDFS files and secondly searching for files through their metadata using Elasticsearch. The work is composed of three parts: The first one is the metadata designer/manager, which is the AngularJS front end. The second part is the J2EE back end which enables the front end to perform all the managing actions on metadata using websockets. The third part is the indexing of data into Elasticsearch, the distributed and scalable open source search engine. Our work has shown that this approach works and it greatly helps finding information in the vast sea of data in the HDFS.