<p align="justify">The main contribution of this thesis is the emphasis made on the reusability concept, on one side, for designing a simulation environment, and on the other side, for defining two different levels of granularity for reusable network component libraries.</p> <p align="justify">The design of our simulation environment, called AMS for Atelier for Modeling and Simulation, was based on existing pieces of software, which proved their usefulness in their respective fields. In order to carry out this integration efficiently, a modular structure of the atelier was proposed. The structure has been divided into four phases. Each phase is responsible of a part of the performance evaluation cycle. The main novelty of this structure is the usage of a dedicated language as a means to define a clear border between the editing and simulation phases and to allow the portability of the atelier upon different platforms. A prototype of the atelier has been developed on a SUN machine running the SunOs operating system. It is developed in C language.</p> <p align="justify">The kernel of the AMS is its library of Detailed Basic Models (DBMs). Each DBM was designed in order to comply with the most important criterion which is reusability. Indeed, each DBM can be used in aeveral network architectures and can be a component of generic and composite models. Before the effective usage of a DBM, it is verified and validated in order to increase the model credibility. The most important contribution of this research is the definition of a methodology for modeling protocol entities as DBMs. We then tried to partly bridge the gap between specification and modeling. This methodology is based on the concept of function. Simple functions are modeled as reusable modules and stored into a library. The Function Based Methodology was designed to help the modeler to build efficiently and rapidly new protocols designed for the new generation of networks where several services can be provided. These new protocols can be dynamically tailored to the user' s requirements.</p>

Les systèmes embarqués sont de plus en plus présents dans notre quotidien, à l’instar des téléphones ou des équipements des voitures modernes. Les systèmes embarqués modernes utilisent des plates-formes de plus en plus complexes. Après avoir longtemps utilisé un seul processeur, les plates-formes modernes peuvent désormais contenir plusieurs processeurs. Depuis quelques années, afin de continuer à améliorer la performance de ces systèmes à moindre coût, certaines de ces plates-formes embarquent désormais plusieurs processeurs différents, parfois même capables de modifier rapidement leurs caractéristiques pendant l’exécution du système. C’est ce qu’on appelle des plates-formes hétérogènes.Cette thèse traite de l’ordonnancement d’applications temps réel strict pour des plates-formes hétérogènes reconfigurables. Établir une polituqe d’ordonnancement consiste à garantir l’exécution d’ensembles de tâches récurrentes, avec le respect des contraintes temporelles de chaque tâche. Dans un contexte de temps réel strict, une tâche doit nécessairement être pleinement exécutée avant son échéance. Tout retard pourrait compromettre la sécurité du système ou des utilisateurs.Produire un ordonnancement temps réel strict efficace pour de telles plates-formes hétérogènes est particulièrement difficile. En effet, la vitesse d’exécution d’un processeur d’une telle plates-forme dépend à la fois du type du processeur et de la tâche exécutée. Cela rend les tâches difficilement interchangeables et augmente ainsi considérablement la complexité des polituqes d’ordonnancement. De plus, le coût d’une migration – le déplacement d’une tâche en cours d’exécution – d’un processeur à un autre est élevé, ce qui peut rendre les polituqes d’ordonnancement peu efficaces en pratique.Dans cette thèse, deux voies sont explorées pour tirer parti des possibilités offertes par ces plates-formes hétérogènes. Tout d’abord, en proposant un ordonnanceur dit global, qui permet une utilisation théorique de l’entièreté de la plates-forme. Pour atteindre cet objectif, nous isolons différents sous-problèmes, en suivant un schéma établi par la littérature existante. Pour chaque sous-problème, nous proposons une amélioration significative par rapport à l’état de l’art. L’ensemble constitue un nouvel ordonnanceur. Une évaluation empirique montre que ses performances sont bien supérieures à celles des ordonnanceurs existants. De plus, la polituqe d’ordonnancement proposée a une meilleure applicabilité, car elle réduit le nombre de migrations d’un processeur à un autre.Une deuxième voie explorée est le paradigme d’application dite multimode. Nous proposons ici le premier modèle où le matériel comme le logiciel peuvent être modifiés pendant l’exécution de l’application, afin de s’adapter au contexte dans lequel elle se trouve. Enfin, deux nouveaux protocoles utilisant ce modèle sont proposés et évalués. Il est montré théoriquement et empiriquement que ces protocoles présentent une faible complexité et de bonnes performances, et correspondent donc au besoin d’applications réelles. / Doctorat en Sciences / info:eu-repo/semantics/nonPublished

Designing a new power electronic conversion system is a multi-step process that requires the R\&D team(s) to go through an extended prototyping phase whose goal is to validate the design in its nominal state, as well as to test its behavior when it is subjected to abnormal conditions. To properly and safely validate all devices that are external to the power stage itself, such as the controllers and the protection systems, one of the best-suited device is a real-time emulator of the converter circuit, a platform that obeys the same mathematical laws and produces the same signals as the original device withoutactually realizing the power conversion. Unfortunately, these models are often based on analog solvers which are difficult to build, must be redesigned for each modification and are subject to drift and aging. While multiple digital real-time emulators have appeared on the market in the last decades, they typically require powerful and expensive computing platforms to perform their calculations or are not generic enough to emulate the more complex power circuits. In this work, we present a new framework that allows the rapid prototyping of a wide range of power converters by translating a power converter schematic drawn on a computer to a real-time equivalent set of equations which is processed by an FPGA with an emulation time-step of less than one microsecond. Contrary to the previously published works, our tools enable the use of entry-level FPGAs even for the emulation circuits composed of twenty switches or more. This framework takes the form of a tool-chain that starts by extracting the necessary information and a standard description from the initial circuit. However, due to the intricate ways in which the switches and diodes can change their state, this raw information is too complex to be processed and emulated directly.Our first major contribution to the state of the art is a way to automatically analyze these changes in order to reduce the complexity of the problem as much as possible while keeping all the necessary information intact. In this thesis, we develop two tools that are able to find all possible changes in the state of the switches that may appear in the immediate future, thereby reducing the quantity of information required to emulate the circuit. Thanks to the global optimization provided by our tools, simulating a typical AC-to-DC converter composed of 12 switches could require 80\% less resources when compared to existing emulators.To enable the emulation or large power converters, we have created a partitioning method which divides the circuit in multiple sub-circuits which are analyzed and optimized separately. The performances of this partitioning are demonstrated by the emulation of a three-phase three-level converter with a relative error of a less that 5% on the signals.To handle our new framework, a dedicated digital platform has been developed. In order to provide the best results even on small FPGAs, particular attention is given to the low resources usage and the low latency of our design. Through multiple examples, we show that this inexpensive real-time emulation platform is able to accurately emulate many circuits in open- or closed-loop operation with a sampling rate higher than 1 MHz / Doctorat en Sciences de l'ingénieur et technologie / info:eu-repo/semantics/nonPublished

Optimisation of Performance Metrics of Embedded Hard Real-Time Systems using Software/Hardware Parallelism. Nowadays, embedded systems are part of our daily lives.Some of these systems are called safetycritical and have strong requirements in terms of safety and reliability.Additionally, these systems must have a long autonomy, good performance and minimal costs.Finally, these systems must exhibit predictable behaviour and provide their results within firm deadlines.When these different constraints are combined in the requirement specifications of a modern product, classic design techniques making use of single core platforms are not sufficient.Academic research in the field of real-time embedded systems has produced numerous techniques to exploit the capabilities of modern hardware platforms.These techniques are often based on using parallelism inherently present in modern hardware to improve the system performance while reducing the platform power dissipation.However, very few systems existing on the market are using these state-of-the-art techniques.Moreover, few of these techniques have been validated in the context of practical experiments.In this thesis, we realise the study of operating system level techniques allowing to exploit hardware parallelism through the implementation of parallel software in order to boost the performance of target applications and to reduce the overall system energy consumption while satisfying strict application timing requirements.We detail the theoretical foundations of the ideas applied in the dissertation and validate these ideas through experimental work.To this aim, we use a new Real-Time Operating System kernel written in the context of the creation of a spin-off of the Université libre de Bruxelles.Our experiments are based on the execution of applications on the operating system which run on a real-world platform for embedded systems.Our results show that, compared to traditional design techniques, using parallel and power-aware scheduling techniques in order to exploit hardware and software parallelism allows to execute embedded applications with substantial savings in terms of energy consumption.We present future and ongoing research work that exploit the capabilities of recent embedded platforms.These platforms combine multi-core processors and reconfigurable hardware logic, allowing further improvements in performance and energy consumption. / Optimisation de Métriques de Performances de Systèmes Embarqués Temps Réel Durs par utilisation du Parallélisme Logiciel et Matériel. De nos jours, les systèmes embarqués font partie intégrante de notre quotidien.Certains de ces systèmes, appelés systèmes critiques, sont soumis à de fortes contraintes de fiabilité et de robustesse.De plus, des contraintes de coûts, d’autonomie et de performances s’additionnent à la fiabilité.Enfin, ces systèmes doivent très souvent respecter des délais très stricts de façon prédictible.Lorsque ces différentes contraintes sont combinées dans le cahier de charge d’un produit, les techniques classiques de conception consistant à utiliser un seul cœur d’un processeur ne suffisent plus.La recherche académique dans le domaine des systèmes embarqués temps réel a produit de nombreuses techniques pour exploiter les plate-formes modernes.Ces techniques sont souvent basées sur l’exploitation du parallélisme inhérent au matériel pour améliorer les performances du système et la puissance dissipée par la plate-forme.Cependant, peu de systèmes existant sur le marché exploitent ces techniques de la littérature et peu de ces techniques ont été validées dans le cadre d’expériences pratiques.Dans cette thèse, nous réalisons l’étude des techniques, au niveau du système d’exploitation, permettant l’exploitation du parallélisme matériel par l’implémentation de logiciels parallèles afin de maximiser les performances et réduire l’impact sur l’énergie consommée tout en satisfaisant les contraintes temporelles strictes du cahier de charge applicatif. Nous détaillons les fondements théoriques des idées qui sont appliquées dans la dissertation et nous les validons par des travaux expérimentaux.A ces fins, nous utilisons le nouveau noyau d’un système d’exploitation écrit dans le cadre de la création d’une spin-off de l’Université libre de Bruxelles.Nos expériences, basées sur l’exécution d’applications sur le système d’exploitation qui s’exécute lui-même sur une plate-forme embarquée réelle, montre que l’utilisation de techniques d’ordonnancement exploitant le parallélisme matériel et logiciel permet de larges économies d’énergie consommée lors de l’exécution d’applications embarquées.De futurs travaux en cours de réalisation sont présentés.Ceux-ci exploitent des plate-formes innovantes qui combinent processeurs multi-cœurs et matériel reconfigurable, permettant d’aller encore plus loin dans l’amélioration des performances et les gains énergétiques. / Doctorat en Sciences / info:eu-repo/semantics/nonPublished

<p align="justify">The main contribution of this thesis is the emphasis made on the reusability concept, on one side, for designing a simulation environment, and on the other side, for defining two different levels of granularity for reusable network component libraries.</p><p><p align="justify">The design of our simulation environment, called AMS for Atelier for Modeling and Simulation, was based on existing pieces of software, which proved their usefulness in their respective fields. In order to carry out this integration efficiently, a modular structure of the atelier was proposed. The structure has been divided into four phases. Each phase is responsible of a part of the performance evaluation cycle. The main novelty of this structure is the usage of a dedicated language as a means to define a clear border between the editing and simulation phases and to allow the portability of the atelier upon different platforms. A prototype of the atelier has been developed on a SUN machine running the SunOs operating system. It is developed in C language.</p><p><p align="justify">The kernel of the AMS is its library of Detailed Basic Models (DBMs). Each DBM was designed in order to comply with the most important criterion which is reusability. Indeed, each DBM can be used in aeveral network architectures and can be a component of generic and composite models. Before the effective usage of a DBM, it is verified and validated in order to increase the model credibility. The most important contribution of this research is the definition of a methodology for modeling protocol entities as DBMs. We then tried to partly bridge the gap between specification and modeling. This methodology is based on the concept of function. Simple functions are modeled as reusable modules and stored into a library. The Function Based Methodology was designed to help the modeler to build efficiently and rapidly new protocols designed for the new generation of networks where several services can be provided. These new protocols can be dynamically tailored to the user' s requirements.</p><p> / Doctorat en sciences appliquées / info:eu-repo/semantics/nonPublished

Cryptography is the foundation of modern IT security,it provides algorithms and protocols that can be usedfor secure communications. Cryptographic algorithmsensure properties such as confidentiality and data integrity.Confidentiality can be ensured using encryption algorithms.Encryption algorithms require a secret information called a key.These algorithms are implemented in cryptographic devices.There exist many types of attacks against such cryptosystems,the main goal of these attacks is the extraction of the secret key.Side-channel attacks are among the strongest types of attacksagainst cryptosystems. Side-channel attacks focus on the attacked device, they measure its physicalproperties in order to extract the secret key. Thus, these attacks targetweaknesses in an implementation of an algorithm rather than the abstract algorithm itself.Power analysis is a type of side-channel attacks that can be used to extract a secretkey from a cryptosystem through the analysis of its power consumption whilethe target device executes an encryption algorithm. We can say that the secret information is leaking from the device through itspower consumption. One of the biggest challenges in the domain of side-channel analysisis the evaluation of a device from the perspective of side-channel attacksor in other words the detection of information leakage.A device can be subject to several sources of information leakageand it is actually relatively easy to find just one side-channel attack that works(by exploiting just one source of leakage),however it is very difficult to find all sources of information leakage or to show that there is no information leakage in the givenimplementation of an encryption algorithm. Evaluators use various statistical tests during the analysis of a cryptographic device to checkthat it does not leak the secret key. However, in order to performsuch tests the evaluation lab needs the device to acquire the measurementsand analyse them. Unfortunately, the development process of cryptographicsystems is rather long and has to go through several stages. Thus, an information leakagethat can lead to a side-channel attackcan be discovered by an evaluation lab at the very last stage using the finalproduct. In such case, the whole process has to be restarted in order to fix the issue,this can lead to significant time and budget overheads. The rationale is that developers of cryptographic systems would like to be able to detect issues related to side-channel analysis during the development of the system,preferably on the early stages of its development. However, it is far from beinga trivial task because the end product is not yet available andthe nature of side-channel attacks is such that it exploits the properties ofthe final version of the cryptographic device that is actually available to the end user. The goal of this work is to show how simulators can be used for the detection of issues related to side-channel analysis during the development of cryptosystems.This work lists the advantages of simulators compared to physical experimentsand suggests a classification of simulators for side-channel analysis.This work presents existing simulators that were created for side-channel analysis,more specifically we show that there is a lack of available simulation toolsand that therefore simulators are rarely used in the domain. We present threenew open-source simulators called Silk, Ascold and Savrasca.These simulators are working at different levels of abstraction,they can be used by developers to perform side-channel analysisof the device during different stages of development of a cryptosystem.We show how Silk can be used during the preliminary analysisand development of cryptographic algorithms using simulations based on high level of abstraction source code. We used it to compare S-boxesas well as to compare shuffling countermeasures against side-channel analysis.Then, we present the tool called Ascold that can be used to find side-channel leakagein implementations with masking countermeasure using the analysis of assembly code of the encryption.Finally, we demonstrate how our simulator called Savrasca can be used to find side-channelleakage using simulations based on compiled executable binaries. We use Savrascato analyse masked implementation of a well-known contest on side-channel analysis (the 4th edition of DPA Contest),as a result we demonstrate that the analysed implementation contains a previouslyundiscovered information leakage. Through this work we alsocompared results of our simulated experiments with real experiments comingfrom implementations on microcontrollers and showed that issues found using our simulatorsare also present in the final product. Overall, this work emphasises that simulatorsare very useful for the detection of side-channel leakages in early stages of developmentof cryptographic systems. / Option Informatique du Doctorat en Sciences / info:eu-repo/semantics/nonPublished