Signal generation at high frequency has become increasingly important in numerous wireline and wireless applications. In many gigahertz and millimeter-wave frequency ranges, conventional frequency generation techniques have encountered several design challenges in terms of frequency tuning range, phase noise, and power consumption. Recently, injection locking has been a popular technique to solve these design challenges for frequency generation. However, the narrow locking range of the injection locking techniques limits their use. Furthermore, they suffer from significant reference spur issues. This dissertation presents novel frequency generation techniques based on envelope detection for low-phase-noise signal generation using injection-locked frequency multipliers (ILFMs). Several calibration techniques using envelope detection are introduced to solve conventional problems in injection locking. The proposed topologies are demonstrated with 0.13um CMOS technology for the following injection-locked frequency generators. First, a mixed-mode injection-frequency locked loop (IFLL) is presented for calibrating locking range and phase noise of an injection-locked oscillator (ILO). The IFLL autonomously tracks the injection frequency by processing the AM modulated envelope signal bearing a frequency difference between injection frequency and ILO free-running frequency in digital feedback. Second, a quadrature injection-locked frequency tripler using third-harmonic phase shifters is proposed. Two capacitively-degenerated differential pairs are utilized for quadrature injection signals, thereby increasing injection-locking range and reducing phase error. Next, an injection-locked clock multiplier using an envelope-based frequency tracking loop is presented for a low phase noise signal and low reference spur. In the proposed technique, an envelope detector constantly monitors the VCO's output waveform distortion caused by frequency difference between the VCO frequency and reference frequency. Therefore, the proposed techniques can compensate for frequency variation of the VCO due to PVT variations. Finally, this dissertation presents a subharmonically injection-locked PLL (SILPLL), which is cascaded with a quadrature ILO. The proposed SILPLL adopts an envelope-detection based injection-timing calibration for synchronous reference pulse injection into a VCO. With one of the largest frequency division ratios (N=80) reported so far, the SILPLL can achieve low RMS jitter and reference spur. / Ph. D. / Signal generation at high frequency has become increasingly important in numerous wireline and wireless applications. In many gigahertz and millimeter-wave frequency ranges, conventional frequency generation techniques have encountered several design challenges in terms of frequency tuning range, phase noise, and power consumption. Recently, injection locking which synchronizes a signal frequency has been a popular technique to solve these design challenges for frequency generation. However, narrow operation ranges of the injection locking techniques limit their use. Furthermore, they suffer from significant noise degradation. This dissertation presents studies of frequency generation techniques based on envelope detection (amplitude modulation) for low-phase-noise signal generation using injection-locked frequency multipliers. Several calibration techniques using envelope detection are introduced to solve conventional problems in injection locking. First, a mixed-mode injection-frequency locked loop is presented for calibrating locking range and phase noise of an injection-locked oscillator. Second, a quadrature injection-locked frequency tripler using third-harmonic phase shifters is proposed to increase injection-locking range and reduce phase error. Third, an injection-locked frequency multiplier using an envelope-based frequency tracking loop is presented for a low phase noise signal and low noise degradation. Finally, this dissertation presents a subharmonically injection-locked PLL with a novel injection-timing calibration circuit, which is connected to a quadrature frequency multiplier. The proposed designs are demonstrated with 0.13µm CMOS technology.