Various methods of estimating the fault probabilities based on defect data of random defects seen in integrated circuit manufacturing are examined. Estimates of fault probabilities based on defect data are less costly than those based on critical area analysis and are potentially more reliable because they are based on actual manufacturing data. Due to limited sample size, means of estimating the confidence interval associated with these estimates are also examined. Because the mathematical expressions associated with defect data-based estimates of the fault probabilities are not amenable to analytical means of obtaining confidence intervals, bootstrapping was employed. The results show that one method of estimating the fault probabilities based on defect data proposed previously is not applicable when using typical in-line data. Furthermore, the results indicate that under typical fab conditions, the assumption of a Poisson random defect distribution gives accurate fault probabilities. The yields as predicted by the fault probabilities estimated from the limited yield concept and kill ratio and those estimated from critical area simulation are shown to be comparable to actual yields observed in the fab. It is also shown that with in-line data, the FP estimated for a given inspection step is a weighted average of the fault probabilities of the defect mechanisms operating at that inspection step. Four bootstrapped based methods of confidence interval estimation for fault probabilities of random defects are examined. The study is based on computer simulation of randomly distributed defects with pre-assigned fault probabilities on dice and the resulting count of different categories of die. The results show that all four methods perform well when the number of fatal defects is reasonably high but deteriorate in performance as the number of fatal defects decrease. The results also show that the BCA (bias-corrected and accelerated) method is more likely to succeed with a smaller number of fatal defects. This success is attributed to its ability to account for change of the standard deviation of the sampling distribution of the FP estimates with the PP of the population, and to account for median bias in the sampling distribution. / Graduation date: 2004

Thesis (M. S.)--Mechanical Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Ume, I. Charles; Committee Member: Mayor, J. Rhett; Committee Member: Sadegh, Nader. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Most current commercial automated IC inspection systems use gray-level or binary images for IC defect detection in spite of the fact that color permits defect detection where gray-level information is insufficient. Three color image processing techniques including the spectral-spatial clustering, principal components, and hue-saturation-value (HSV) color features have been investigated to evaluate the usefulness of color for IC defect detection. The AMOEBA spectral-spatial clustering algorithm, an un-supervised color segmentation approach, with a sequence of image processing procedures resulted in segmentation results with high accuracy and discriminated successfully an isolated and homogeneous defect with an unique color signature. The principal components transformation and the HSV color features, two color enhancement/separation algorithms, have proven useful for enhancing and isolating weak spectral signatures in the defect regions. The results of this investigation into the use of color are promising.

This dissertation describes a new simulation technique for an automatic test generation system, SCIRTSS version 4.0 (Sequential Circuit Test Sequence System). This test generation system is driven by the hardware compiler AHPL, a Hardware Programming Language, and an intelligent heuristic-based search for test vector generation. Using a fault-injection gate-level simulator and the generated test vector, all the faulty states of the circuit are simulated in parallel and the simulator is thus able to find all detected faults by a particular input sequence. The major objective of this research was to develop a faster replacement for the existing simulation process. The philosophy of divide and conquer is used in the development of the new simulation technique. Sequential networks are divided into combinational sub-networks, and, if necessary, the combinational sub-networks are further reduced into fan-out free regions. Thus, the problem is reduced to a relatively simple combinational one. In addition to the classical faults, the new simulator attempts to detect CMOS stuck-open faults. Several circuits were tested under SCIRTSS 4.0 using both the existing and the new simulation techniques. The results are listed in this paper to verify superiority of the new simulation technique.

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The long-term goal of this research is to assist in the development of a fast, accurate, and low-cost nondestructive inspection prototype for solder joints in integrated circuits (IC). The goal of the work described in this thesis is to develop a fully automated system to maintain the signal strength of the vibrometer that would reduce the testing time while maintaining or improving the quality of the defect detection results. The ability to perform the inspections in an automated manner is very important in order to demonstrate the ability of the defect detection system to be used for online inspection without the need of an operator. The system was able to find the maximum signal strength (at a single point on the surface of a flip chip) nearly five times faster than Polytec's commercial system with a search time of approximately 2.1 sec. When integrated into the nondestructive inspection prototype, the system described in this work was found to approximately reduce the data acquisition time per test location by four times, with a minimum data acquisition time of 8.5 sec and an average time of 15.4 sec, while maintaining the same level of quality of results obtained by a skilled operator when manually maintaining the signal strength of the vibrometer. Hardware was developed that retrofitted a vibrometer's focusing head at the end of a fiber optic cable to a motorized linear stage. This stage controlled the standoff distance between the focusing head and the IC's surface with a fixed focal length, which allowed the spot size of the laser to be adjusted while searching for a desired signal strength. Numerous tests were conducted to determine the search parameters, which led to a search time of approximately 2.1 sec. This time was found to be dependent on the surface finish of the IC being inspected. It was also found that to achieve a desired signal intensity strength, not only does the standoff height of the focusing head, which determines the laser spot size, need to be controlled, but also the exact location on which the laser is reflecting off the IC.

This work presents introductory research to provide the relationship between electrical measurements and residual stresses caused by hybrid processing. X-ray diffraction is used to measure residual stresses in the ceramic substrate as well as metallization of wideband coplanar thick film probes. The probes are also tested for electrical performance using Time Domain Reflectometry (TDR) technique. This thesis presents results that indicate that significant tensile residual stresses were generated on the back of the substrate, particularly during the laser scribing phase of the finished device. Significant tensile stresses were also observed in the Silver-Palladium (Ag-Pd) metallization. TDR measurements indicated significant response variations which were attributed to these induced stresses. Attempts were also made to reduce these stresses by an annealing process in order to improve the TDR response uniformity. / Master of Science

This thesis presents a statistical method to identify the test escapes. Test often acquires parametric measurements as a function of logical state of a chip. The usual method of classifying chips as pass or fail is to compare each state measurement to a test limit. Subtle manufacturing defects are escaping the test limits due to process variations in deep sub-micron technologies which results in mixing of healthy and faulty parametric test measurements. This thesis identifies the chips with subtle defects by using rank order of the parametric measurements. A hypothesis is developed that a defect is likely to disturb the defect-free ranking, whereas a shift caused by process variations will not affect the rank. The hypothesis does not depend on a-priori knowledge of a defect-free ranking of parametric measurements. This thesis introduces a modified Estimation Maximization (EM) algorithm to separate the healthy and faulty tau components calculated from parametric responses of die pairs on a wafer. The modified EM uses generalized beta distributions to model the two components of tau mixture distribution. The modified EM estimates the faulty probability of each die on a wafer. The sensitivity of the modified EM is evaluated using Monte Carlo simulations. The modified EM is applied on production product A. An average 30% reduction in DPPM (defective parts per million) is observed in Product A across all lots.