by Ronald Siu-kwong, Ip. / "June 1999." / Thesis (Ph.D.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (p. 89-94). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Two dimensional (2D) materials have been explosively researched since the discovery of graphene but the applications of 2D materials have been extremely constrained because of a variety of shortcomings in the materials such as zero bandgap in graphene or defective growth techniques for wide-bandgap materials. Nonetheless, such novel materials are very promising in the doomed situation which Moore’s law keeps slowing down. Graphene and αMoO3 have been particularly of interest because graphene has developed large-scale growth methods and αMoO3 has wide bandgap. In case of graphene, searching for the applications with zero bandgap has been important and in the other, αMoO3 has not been developed for large-scale growth techniques yet even though the applications are strongly expected to be developed. In this thesis, unconventional CVD graphene electronics and large scale αMoO3 synthesis have been studied for very large scale integration (VLSI). A 512 flexible graphene voltage amplifier array and the highest peak-to-valley current ratio NDR devices emitting green color in graphene nanogap are presented so that large-scale CMOS compatible circuit integration can be available for bio and RF (radio frequency) applications. Having 2.8eV bandgap, a large-scale growth method for αMoO3 is developed for the first time showing ambipolar and memristive behaviors.

For the congestion issue, we found that the existing congestion models will very often over-estimate the congestion at the densely routed regions because real routers will perform rip-up and re-route operations and route the nets with detour to avoid overflow. We propose a 3-step approach that is designed to tackle this problem. It can simulate the global routing, detailed routing and rip-up and re-route process in the real routing procedure. Results show that the prediction accuracy can be improved by 30%. In addition, we have also implemented a routability-driven floorplanner with our congestion model. Results show that the number of un-routable wires can be reduced if the number of overflow tiles can be reduced during floorplanning. Then we studied and developed two post-processing steps to be applied on an interconnect optimized floorplan or placement to further reduce the total wirelength or area. For the wirelength issue, we presented an elegant solution to the cell flipping problem. We presented a detailed study of this cell flipping problem in a placement result to reduce interconnect length. We find the optimal flipping of the cells by formulating the cell flipping problem as a mixed integer linear programming problem to give the shortest total wirelength. In order to reduce the runtime, we proposed a cell orientation fixing step to fix the orientations of some cells. Results show that we can obtain optimal result by solving the mixed integer linear programming problem of the remaining variables directly or the problem can be solved by linear programming such that we can still obtain a result very close to the optimal solution with a much shorter runtime. For area reduction on an interconnect optimized floorplan, we proposed a new approach called deadspace utilization to reduce the total area of an interconnect optimized floorplan by making use of the shape flexibility of some modules. Results show that we can apply this deadspace utilization technique to reduce the area and wirelength of the original floorplan further, subject to the constraint of maintaining the routability and congestion of the original floorplan. / We have studied several interconnect-related optimization problems in floor-planning and placement of VLSI circuits in details. When the number of small logic gates is large in a circuit design, good netlist designs may still result in poor layouts because of various interconnect problems. Most of the problems cannot be fixed manually today because of the incomprehensible circuit complexity. Design automation techniques on interconnect issues in physical design of VLSI circuits becomes indispensable. Recently, congestion minimization and wirelength optimization are two hot topics in interconnect planning. / Sham Chiu Wing. / "March 2006." / Adviser: Young Fung Yu. / Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6634. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 106-115). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Lai Tsz Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 123-129). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Cycle --- p.2 / Chapter 1.2 --- Physical Design Cycle --- p.4 / Chapter 1.3 --- Floorplanning --- p.7 / Chapter 1.3.1 --- Types of Floorplan and Floorplan Representations --- p.11 / Chapter 1.3.2 --- Interconnect-driven Floorplanning --- p.13 / Chapter 1.4 --- Motivations and Contributions --- p.17 / Chapter 1.5 --- Organization of this Thesis --- p.18 / Chapter 2 --- Literature Review on Floorplan Representation --- p.20 / Chapter 2.1 --- Slicing Floorplan Representation --- p.20 / Chapter 2.1.1 --- Normalized Polish Expression --- p.20 / Chapter 2.2 --- Non-slicing Floorplan Representations --- p.21 / Chapter 2.2.1 --- Sequence Pair (SP) --- p.21 / Chapter 2.2.2 --- Bounded-sliceline Grid (BSG) --- p.23 / Chapter 2.2.3 --- O-tree --- p.25 / Chapter 2.2.4 --- B*-tree --- p.26 / Chapter 2.3 --- Mosaic Floorplan Representations --- p.28 / Chapter 2.3.1 --- Corner Block List (CBL) --- p.28 / Chapter 2.3.2 --- Twin Binary Trees (TBT) --- p.31 / Chapter 2.3.3 --- Twin Binary Sequences (TBS) --- p.32 / Chapter 2.4 --- Summary --- p.34 / Chapter 3 --- Literature Review on Interconnect Optimization in Floorplan- ning --- p.37 / Chapter 3.1 --- Wirelength Estimation --- p.37 / Chapter 3.2 --- Congestion Optimization --- p.38 / Chapter 3.2.1 --- Integrated Floorplanning and Interconnect Planning --- p.41 / Chapter 3.2.2 --- Multi-layer Global Wiring Planning (GWP) --- p.43 / Chapter 3.2.3 --- Estimating Routing Congestion using Probabilistic Anal- ysis --- p.44 / Chapter 3.2.4 --- Congestion Minimization During Placement --- p.46 / Chapter 3.2.5 --- Modelling and Minimization of Routing Congestion --- p.48 / Chapter 3.3 --- Buffer Planning --- p.49 / Chapter 3.3.1 --- Buffer Clustering with Feasible Region --- p.51 / Chapter 3.3.2 --- Routability-driven Repeater Clustering Algorithm with Iterative Deletion --- p.55 / Chapter 3.3.3 --- Planning Buffer Locations by Network Flow --- p.58 / Chapter 3.3.4 --- Buffer Planning using Integer Multicommodity Flow --- p.60 / Chapter 3.3.5 --- Buffer Planning Problem using Tile Graph --- p.60 / Chapter 3.3.6 --- Probabilistic Analysis for Buffer Block Planning --- p.62 / Chapter 3.3.7 --- Fast Buffer Planning and Congestion Optimization --- p.63 / Chapter 3.4 --- Summary --- p.66 / Chapter 4 --- Congestion Evaluation: Wire Density Model --- p.68 / Chapter 4.1 --- Introduction --- p.68 / Chapter 4.2 --- Overview of Our Floorplanner --- p.70 / Chapter 4.3 --- Wire Density Model --- p.71 / Chapter 4.3.1 --- Computation of Ni --- p.72 / Chapter 4.3.2 --- Computation of Pi --- p.74 / Chapter 4.3.3 --- Usage of Mirror TBT --- p.76 / Chapter 4.4 --- Implementation --- p.76 / Chapter 4.4.1 --- Efficient Calculation of Ni --- p.76 / Chapter 4.4.2 --- Solving the LCA Problem Efficiently --- p.81 / Chapter 4.4.3 --- Cost Function --- p.81 / Chapter 4.4.4 --- Complexity --- p.81 / Chapter 4.5 --- Experimental Results --- p.82 / Chapter 4.6 --- Conclusion --- p.83 / Chapter 5 --- Buffer Planning: Simple Buffer Planning Method --- p.85 / Chapter 5.1 --- Introduction --- p.85 / Chapter 5.2 --- Variable Interval Buffer Insertion Constraint --- p.87 / Chapter 5.3 --- Overview of Our Floorplanner --- p.88 / Chapter 5.4 --- Buffer Planning --- p.89 / Chapter 5.4.1 --- Feasible Grids --- p.89 / Chapter 5.4.2 --- Table Look-up Approach --- p.89 / Chapter 5.5 --- Implementation --- p.91 / Chapter 5.5.1 --- Building the Look-up Tables --- p.91 / Chapter 5.5.2 --- An Example of Look-up Table Construction --- p.94 / Chapter 5.5.3 --- A Faster Approach for Building the Look-up Tables --- p.101 / Chapter 5.5.4 --- An Example of the Faster Look-up Table Construction --- p.105 / Chapter 5.5.5 --- I/O Pin Locations --- p.106 / Chapter 5.5.6 --- Cost Function --- p.110 / Chapter 5.5.7 --- Complexity --- p.111 / Chapter 5.6 --- Experimental Results --- p.112 / Chapter 5.6.1 --- Selected Value for A --- p.112 / Chapter 5.6.2 --- Performance of Our Floorplanner --- p.113 / Chapter 5.7 --- Conclusion --- p.116 / Chapter 6 --- Conclusion --- p.118 / Chapter A --- An Efficient Algorithm for the Least Common Ancestor Prob- lem --- p.120 / Bibliography --- p.123

Wong Sze Hon. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 88-91). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Preliminaries --- p.1 / Chapter 1.2 --- Motivations --- p.1 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Organization of the Thesis --- p.4 / Chapter 2 --- VLSI Physical Design Automation --- p.5 / Chapter 2.1 --- Preliminaries --- p.5 / Chapter 2.2 --- VLSI Design Cycle [1] --- p.6 / Chapter 2.2.1 --- System Specification --- p.6 / Chapter 2.2.2 --- Architectural Design --- p.6 / Chapter 2.2.3 --- Functional Design --- p.6 / Chapter 2.2.4 --- Logic Design --- p.8 / Chapter 2.2.5 --- Circuit Design --- p.8 / Chapter 2.2.6 --- Physical Design --- p.8 / Chapter 2.2.7 --- Fabrication --- p.8 / Chapter 2.2.8 --- Packaging and Testing --- p.9 / Chapter 2.3 --- Physical Design Cycle [1] --- p.9 / Chapter 2.3.1 --- Partitioning --- p.9 / Chapter 2.3.2 --- Floorplanning and Placement --- p.11 / Chapter 2.3.3 --- Routing --- p.11 / Chapter 2.3.4 --- Compaction --- p.12 / Chapter 2.3.5 --- Extraction and Verification --- p.12 / Chapter 2.4 --- Chapter Summary --- p.12 / Chapter 3 --- Recent Approaches on Circuit Partitioning --- p.14 / Chapter 3.1 --- Preliminaries --- p.14 / Chapter 3.2 --- Circuit Representation --- p.15 / Chapter 3.3 --- Delay Modelling --- p.16 / Chapter 3.4 --- Partitioning Objectives --- p.19 / Chapter 3.4.1 --- Interconnections between Partitions --- p.19 / Chapter 3.4.2 --- Delay Minimization --- p.19 / Chapter 3.4.3 --- Area and Number of Partitions --- p.20 / Chapter 3.5 --- Partitioning Algorithms --- p.20 / Chapter 3.5.1 --- Cut-size Driven Partitioning Algorithm --- p.21 / Chapter 3.5.2 --- Delay Driven Partitioning Algorithm --- p.32 / Chapter 3.5.3 --- Acyclic Circuit Partitioning Algorithm --- p.33 / Chapter 4 --- Clustering Based Acyclic Multi-way Partitioning --- p.38 / Chapter 4.1 --- Preliminaries --- p.38 / Chapter 4.2 --- Previous Works on Clustering Based Partitioning --- p.39 / Chapter 4.2.1 --- Multilevel Circuit Partitioning [2] --- p.40 / Chapter 4.2.2 --- Cluster-Oriented Iterative-Improvement Partitioner [3] --- p.42 / Chapter 4.2.3 --- Section Summary --- p.44 / Chapter 4.3 --- Problem Formulation --- p.45 / Chapter 4.4 --- Clustering Based Acyclic Multi-Way Partitioning --- p.46 / Chapter 4.5 --- Modified Fan-out Free Cone Decomposition --- p.47 / Chapter 4.6 --- Clustering Phase --- p.48 / Chapter 4.7 --- Partitioning Phase --- p.51 / Chapter 4.8 --- The Acyclic Constraint --- p.52 / Chapter 4.9 --- Experimental Results --- p.57 / Chapter 4.10 --- Chapter Summary --- p.58 / Chapter 5 --- Network Flow Based Multi-way Partitioning --- p.61 / Chapter 5.1 --- Preliminaries --- p.61 / Chapter 5.2 --- Notations and Definitions --- p.62 / Chapter 5.3 --- Net Modelling --- p.63 / Chapter 5.4 --- Previous Works on Network Flow Based Partitioning --- p.64 / Chapter 5.4.1 --- Network Flow Based Min-Cut Balanced Partitioning [4] --- p.65 / Chapter 5.4.2 --- Network Flow Based Circuit Partitioning for Time-multiplexed FPGAs [5] --- p.66 / Chapter 5.5 --- Proposed Net Modelling --- p.70 / Chapter 5.6 --- Partitioning Properties Based on the Proposed Net Modelling --- p.73 / Chapter 5.7 --- Partitioning Step --- p.75 / Chapter 5.8 --- Constrained FM Post Processing Step --- p.79 / Chapter 5.9 --- Experiment Results --- p.81 / Chapter 6 --- Conclusion --- p.86 / Bibliography --- p.88

Li, Liang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references (leaves 57-61). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.1.1 --- Partitioning --- p.1 / Chapter 1.1.2 --- Floorplanning and Placement --- p.2 / Chapter 1.1.3 --- Routing --- p.2 / Chapter 1.1.4 --- Compaction --- p.3 / Chapter 1.2 --- Motivations --- p.3 / Chapter 1.3 --- Problem Formulation --- p.4 / Chapter 1.3.1 --- Properties of OARSMT --- p.4 / Chapter 1.4 --- Progress on the Problem --- p.4 / Chapter 1.5 --- Contributions --- p.5 / Chapter 1.6 --- Thesis Organization --- p.6 / Chapter 2 --- Literature Review on OARSMT --- p.8 / Chapter 2.1 --- Introduction --- p.8 / Chapter 2.2 --- Previous Methods --- p.9 / Chapter 2.2.1 --- OARSMT --- p.9 / Chapter 2.2.2 --- Shortest Path Problem with Blockages --- p.13 / Chapter 2.2.3 --- OARSMT with Delay Minimization --- p.14 / Chapter 2.2.4 --- OARSMT with Worst Negative Slack Maximization --- p.14 / Chapter 2.3 --- Comparison --- p.15 / Chapter 3 --- Heuristic Method --- p.17 / Chapter 3.1 --- Introduction --- p.17 / Chapter 3.2 --- Our Approach --- p.18 / Chapter 3.2.1 --- Handling of Multi-pin Nets --- p.18 / Chapter 3.2.2 --- Propagation --- p.20 / Chapter 3.2.3 --- Backtrack --- p.23 / Chapter 3.2.4 --- Finding MST --- p.26 / Chapter 3.2.5 --- Local Refinement Scheme --- p.26 / Chapter 3.3 --- Experimental Results --- p.28 / Chapter 3.4 --- Summary --- p.28 / Chapter 4 --- Exact Method --- p.32 / Chapter 4.1 --- Introduction --- p.32 / Chapter 4.2 --- Review on GeoSteiner --- p.33 / Chapter 4.3 --- Overview of our Approach --- p.33 / Chapter 4.4 --- FST with Virtual Pins --- p.34 / Chapter 4.4.1 --- Definition of FST --- p.34 / Chapter 4.4.2 --- Notations --- p.36 / Chapter 4.4.3 --- Properties of FST with Virtual Pins --- p.36 / Chapter 4.5 --- Generation of FST with Virtual Pins --- p.46 / Chapter 4.5.1 --- Generation of FST with Two Pins --- p.46 / Chapter 4.5.2 --- Generation of FST with 3 or More Pins --- p.48 / Chapter 4.6 --- Concatenation of FSTs with Virtual Pins --- p.50 / Chapter 4.7 --- Experimental Results --- p.52 / Chapter 4.8 --- Summary --- p.53 / Chapter 5 --- Conclusion --- p.55 / Bibliography --- p.61

Ma, Tilen. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 98-100). / Abstracts in English and Chinese. / Abstract --- p.i / Chapter 0.1 --- Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Physical Design Cycle --- p.2 / Chapter 1.2 --- Floorplanning --- p.6 / Chapter 1.2.1 --- Floorplanning Objectives --- p.7 / Chapter 1.2.2 --- Common Approaches --- p.8 / Chapter 1.3 --- Motivations and Contributions --- p.11 / Chapter 1.4 --- Organization of the Thesis --- p.13 / Chapter 2 --- Literature Review on Placement Constraints in Floorplanning --- p.15 / Chapter 2.1 --- Introduction --- p.15 / Chapter 2.2 --- Algorithms for Abutment Constraint --- p.16 / Chapter 2.3 --- Algorithms for Alignment Constraint --- p.18 / Chapter 2.4 --- Algorithms for Boundary Constraint --- p.20 / Chapter 2.5 --- Unified Approach for Placement Constraints --- p.23 / Chapter 2.5.1 --- Representation of Placement Constraints --- p.23 / Chapter 2.5.2 --- Handling Relative Placement Constraints --- p.24 / Chapter 2.5.3 --- Examples for Handling Placement Constraints --- p.25 / Chapter 3 --- Literature Review on Bus-Driven Floorplanning --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- Previous Work --- p.28 / Chapter 3.2.1 --- Zero-Bend Bus-Driven Floorplanning [3] --- p.28 / Chapter 3.2.2 --- Two-Bend Bus-Driven Floorplanning [1] --- p.32 / Chapter 4 --- Placement Constraints for Multi-Bend Bus in TCGs --- p.38 / Chapter 4.1 --- Introduction --- p.38 / Chapter 4.2 --- Transitive Closure Graph [6] --- p.39 / Chapter 4.3 --- Placement Constraints for Zero-Bend Bus --- p.41 / Chapter 4.4 --- Placement Constraints for Multi-Bend Bus --- p.44 / Chapter 4.5 --- Placement Constraints for Bus Ordering --- p.45 / Chapter 4.5.1 --- Natural Bus Ordering in TCGs --- p.45 / Chapter 4.5.2 --- Explicit Bus Ordering in TCGs --- p.46 / Chapter 5 --- TCG-Based Bus-Driven Floorplanning --- p.48 / Chapter 5.1 --- Motivation --- p.48 / Chapter 5.2 --- Problem Formulation --- p.49 / Chapter 5.3 --- Methodology --- p.50 / Chapter 5.3.1 --- Construction of Reduced Graphs --- p.51 / Chapter 5.3.2 --- Construction of Common Graph --- p.52 / Chapter 5.3.3 --- Spanning Tree for Bus Assignment --- p.53 / Chapter 5.3.4 --- Formation of Bus Components --- p.55 / Chapter 5.3.5 --- Bus Feasibility Check --- p.56 / Chapter 5.3.6 --- Overlap Removal --- p.57 / Chapter 5.3.7 --- Floorplan Realization --- p.58 / Chapter 5.3.8 --- Simulated Annealing --- p.58 / Chapter 5.3.9 --- Soft Module Adjustment --- p.60 / Chapter 5.4 --- Experimental Results --- p.60 / Chapter 5.5 --- Summary --- p.65 / Chapter 6 --- Conclusion --- p.67 / Chapter A --- Appendix --- p.69 / Chapter A.1 --- Well-Known Algorithms --- p.69 / Chapter A.1.1 --- Kruskal's Algorithm --- p.69 / Chapter A.1.2 --- Bellman-Ford Algorithm --- p.69 / Chapter A.2 --- Figures of Resulting Floorplans --- p.71 / Chapter A.2.1 --- Data Set One --- p.71 / Chapter A.2.2 --- Data Set Two --- p.80 / Chapter A.2.3 --- Data Set Three --- p.85 / Chapter A.2.4 --- Data Set Four --- p.92 / Bibliography --- p.98

Bibliography: leaves 282-296.

In this dissertation, multi-rate array (MRA) architecture and its synthesis are proposed and developed. Using multi-coordinate systems (MCS), a unified theory for mapping algorithms from their original algorithmic specifications onto multi-rate arrays is developed. A multi-rate array is a grid of processors in which each interconnection may have its own clock rate; operations with different complexities run at their own clock rate, thus increasing the throughput and efficiency. A class of algorithms named directional affine recurrence equations (DARE) is defined. The dependence space of a DARE can be decomposed into uniform and non-uniform subspaces. When projected along the non-uniform subspace, the resultant array structure is regular. Limitations and restrictions of this approach are investigated and a procedure for mapping DARE onto MRA is developed. To generalize this approach, synthesis theory is developed with initial specification as affine direct input output (ADIO) which aims at removing redundancies from algorithms. Most ADIO specifications are the original algorithmic specifications. A multi-coordinate systems (MCS) is used to present an algorithm's dependence structures. In a MCS system, the index spaces of the variables in an algorithm are defined relative to their own coordinate systems. Most traditionally considered irregular algorithms present regular dependence structures under MCS technique. Procedures are provided for transforming algorithms from original algorithmic specifications to their regular specifications. Multi-rate schedules and multi-rate timing functions are studied. The solution for multi-rate timing functions can be formulated as linear programming problems. Procedures are provided for mapping ADIOs onto multi-rate VLSI systems. Examples are provided to illustrate the synthesis of MRAs from DAREs and ADIOs. The first major contribution of this dissertation is the development of the concrete, executable MRA architectures. The second is the introduction of MCS system and its application in the development of the theory for synthesizing MRAs from original algorithmic specifications. / Graduation date: 1995

M.S. / Computer Science & Engineering / Some biological aspects of neural interactions are presented and used as a basis for a computational model in the development of a new type of computer architecture. A VLSI microarchitecture is proposed that efficiently implements the neural-based computing methods. An analysis of the microarchitecture is presented to show that it is feasible using currently available VLSI technology. The performance expectations of the proposed system are analyzed and compared to conventional computer systems executing similar algorithms. The proposed system is shown to have comparatively attractive performance and cost/performance ratio characteristics. Some discussion is given on system level characteristics including initialization and learning.