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The Global ETD Search service is a free service for researchers
to find electronic theses and dissertations. This service is
provided by the
Networked Digital Library of Theses and Dissertations.
Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
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Showing 61 to 70 of 217 (0.082 seconds)Spelling suggestions: "subject:"entegrated circuits very large scale"" "subject:"entegrated circuits nery large scale""
| 61 |
Synthesis of biological vision models using analog VLSI / Alireza Moini.Moini, Alireza January 1997 (has links)
Bibliography: leaves 195-210. / xviii, 210 leaves : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / A systematic view of all design levels, from the pixie level to the architectural level of vision chips. Important issues in the design of analog VLSI (AVLSI) vision chips, including mismatch and digital noise are addressed. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1998
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| 62 |
Passivity checking and enforcement in VLSI model reduction exerciseLiu, Yansong. January 2008 (has links)
Thesis (M. Phil.)--University of Hong Kong, 2008. / Includes bibliographical references (leaf 95-101) Also available in print.
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| 63 |
Another approach to PLA foldingTan, Chong Guan January 1985 (has links)
No description available.
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| 64 |
An efficient single-latch scan-design scheme/Panda, Uma R. January 1985 (has links)
No description available.
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| 65 |
A linear unification processor /Hum, Herbert Hing-Jing January 1987 (has links)
No description available.
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| 66 |
Unsorted VLSI dictionary machinesSomani, Arun K. (Arun Kumar) January 1983 (has links)
No description available.
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| 67 |
A MOS delay model for switch-level simulation /Peckel, Marcos David. January 1985 (has links)
No description available.
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| 68 |
A cluster-proof approach to yield enhancement of large area binary tree architectures /Howells, Michael C. January 1987 (has links)
No description available.
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| 69 |
Timing analysis for MOSFETS, an integrated approachDagenais, Michel R. January 1987 (has links)
No description available.
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| 70 |
Using N.2 to Model a Microprocessor SystemPatz, Benjamin J. 01 January 1985 (has links) (PDF)
Due to the complexity of designing digital systems using VLSI parts, a tool for aiding in system level design specification and verification is needed. Functional level modeling languages and simulators provide that tool. An example of such a tool is the N.2 package of software produced by Endot Inc. and soon to be running on a VAX computer at the University of Central Florida. An overview of the N.2 system is presented in this paper with emphasis on the modeling language of N.2, ISP’. A Small Instruction set Computer (SIC), originally specified in HAPL, is designed with this software using several design methodologies. These range from an instruction level implementation to a microcoded register level implementation. The ISP’ source code is provided for each implementation. Comments on the ability of the N.2 software to model systems at various levels of design abstraction are made. A comparison of the functional modeling language of N.2, ISP’ to other functional level design languages is made. Finally, some areas that warrant further investigation are presented.
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