A methodology for the automatic translation of a Hardware Description Language (HDL) formulation of a VLSI system to a structured array-type of target realization is the subject of this investigation. A particular combination of input HDL and target technology has been implemented as part of the exercise, and a detailed evaluation of the result is presented. The HDL used in the study is AHPL, a synchronous clock-mode language which accepts the description of the hardware at Register Transfer Level. The target technology selected is Storage Logic Array (SLA), an evolution of PLA concept. Use of the SLA has a distinct advantage, notably in the ability to sidestep the interconnection routing problem, an expensive and time-consuming process in normal IC design. Over the past years, an enormous amount of effort has gone into generation of layout from an interconnection list. This conventional approach seems to complicate the placement and routing processes in later stages. In this research project the major emphasis has therefore been on extracting relevant global information from the higher-level description to guide the subsequent placement and routing algorithms. This effectively generates the lower-level layout directly from higher-level description. A special version of AHPL compiler (stage 3) has been developed as part of the project. The SLA data structure formats and the implementation of the Data and Control Sections of the target are described in detail. Also the evaluation and possibilities for future research are discussed.

Reducing circuit complexity to minimize design turnaround time and maximize chip area utilization is the most evident problem in dealing with VLSI layout. Three suggestions have been recommended to reduce circuit complexity. They are using regular modules as design targets, using hierarchical top-down design as a design methodology, and using CAD as a design tool. These three suggestions are the basis of this dissertation project. In this dissertation, three silicon compilers were implemented which take an universal AHPL circuit description as an input and automatically translate it into SLA (Storage Logic Array), PPLA (Path Programmable Logic Array), and ULA (Uncommitted Logic Array) chip layout. The goal is to study different layout algorithms and to derive better algorithms for alternative VLSI structures. In order to make a precise chip area comparison of these three silicon compilers, real SLA and ULA circuits have been designed. Four typical AHPL descriptions of different circuits or varying complexity were chosen as comparison examples. The result shows that the SLA layout requires least area for circuit realization generally. The PPLA approach is the worst one for large scale circuit realization, while the ULA lies in between.

No description available.

With electronic packaging becoming more complex, simple hand methods to model the thermal performance of the package are insufficient. As computer aided modeling methods came into use, a test system was developed to verify the predictions produced by such modeling methods. The test system is evaluated for operation and performance. Further, the premise of this type of test (the accurate calibration of packaged temperature-sensitive-parameter devices can be done) is investigated using a series of comparative tests. From this information, causes of possible/probable errors in calibration are identified and related to the different methodologies and devices used. Finally, conclusions are presented regarding the further improvement of the test system and methodologies used in this type of testing.

In a VLSI design environment, a more efficient test generation algorithm is definitely needed. This thesis evaluates a test generation algorithm, PODEM, as mechanism to generate the goal states in a sequential circuit test search system, SCIRTSS. First, a hardware description language, AHPL, is used to describe the behavior of a sequential circuit. Next, SCIRTSS is used to generate the test vectors. Several circuits are evaluated and experimental results are compared with data from a previous version of SCIRTSS which was implemented with the D-Algorithm. Depending on the number of reconvergent fanouts in a circuit, it is found that PODEM is 1 to 23 times faster than the D-Algorithm.

In this thesis, the gate matrix layout problem in VLSI design is considered where the goal is to minimize the number of tracks required to layout a given circuit and a taxonomy of approaches to its solution is presented. An efficient hybrid heuristic is also proposed for this combinatorial optimization problem, which is based on the combination of probabilistic hill-climbing technique and greedy method. This heuristic is tested experimentally with respect to four existing algorithms. As test cases, five benchmark problems from the literature as well as randomly generated problem instances are considered. The experimental results show that the proposed hybrid algorithm, on the average, performs better than other heuristics in terms of the required computation time and/or the quality of solution. Due to the computation-intensive nature of the problem, an exact solution within reasonable time limits is impossible. So, it is difficult to judge the effectiveness of any heuristic in terms of the quality of solution (number of tracks required). A probabilistic model of the gate matrix layout problem that computes the expected number of tracks from the given input parameters, is useful to this respect. Such a probabilistic model is proposed in this thesis, and its performance is experimentally evaluated.

This dissertation studies two independent problems, one is about graph labeling and the other problem is related to connectivity condition in a simple graph. Graph labeling is a rapidly developing area of research in graph theory, having connections with a variety of application-oriented areas such as VLSI optimization, data structures and data representation. Furthermore, the connectivity conditions in a simple graphs may help us to study the new aspects of ad hoc networks, social networks and web graphs. In chapter 2, we study path systems, reduced path systems and how to construct a super edge-graceful tree with any number of edges using path systems. First, we give an algorithm to reduce a labeled path system to a smaller labeled path system of a different type. First, we investigate the cases (m, k) = (3; 5) and (m, k) = (4; 7), where m is the number of paths and 2k is the length of each path, and then we give a generalization for any k, m = 3 and m = 4. We also describe a procedure to construct a super-edge-graceful tree with any number of edges. / Includes bibliography. / Dissertation (Ph.D.)--Florida Atlantic University, 2014. / FAU Electronic Theses and Dissertations Collection

by Teresa W.M. Ng. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1989. / Bibliography: leaves 97-100.

by Sau-yuen Wong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 77-82). / Acknowledgement --- p.i / Abstract --- p.ii / List of Tables --- p.ii / List of Figures --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Review of Previous Work --- p.4 / Chapter 2.1 --- Optimization of Delay and Layout Design --- p.4 / Chapter 2.2 --- Simulated Annealing --- p.8 / Chapter 3 --- Definition of Circuit Model --- p.12 / Chapter 4 --- Evaluation of Delay --- p.16 / Chapter 4.1 --- RC-tree and Elmore Delay --- p.16 / Chapter 4.2 --- Exponential Decayed Polynomial Function --- p.17 / Chapter 4.3 --- Two-pole Approximation --- p.18 / Chapter 4.4 --- AWE and Adopted Delay Model --- p.19 / Chapter 5 --- Delay Minimization by Simulated Annealing --- p.28 / Chapter 5.1 --- Cost Function --- p.28 / Chapter 5.2 --- Neighbor Moves --- p.30 / Chapter 5.2.1 --- Logical models --- p.31 / Chapter 5.2.2 --- Discretization of Solution Space --- p.32 / Chapter 5.2.3 --- Valid Configurations --- p.35 / Chapter 5.2.4 --- Valid Moves --- p.39 / Chapter 5.2.5 --- Modification to the Newly Generated Graph --- p.41 / Chapter 5.2.6 --- Access to Neighbor configuration --- p.43 / Chapter 5.2.7 --- Reduction of Solution Space --- p.45 / Chapter 5.2.8 --- Correctness of the Algorithm --- p.48 / Chapter 5.2.9 --- Completeness of the Algorithm --- p.49 / Chapter 6 --- Experimental result --- p.56 / Chapter 6.1 --- Optimization of Overall Performance --- p.58 / Chapter 6.2 --- Optimization on Individual Delay --- p.70 / Chapter 7 --- Conclusion --- p.74 / A --- p.76 / Bibliography

by Eva Yuk-Wah Pang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1995. / Includes bibliographical references (leaves 88-89). / ACKNOWLEDGEMETS / ABSTRACT / LIST OF FIGURES / LIST OF TABLES / Chapter CHAPTER1 --- INTRODUCTION / Chapter 1.1 --- Motivation --- p.1-1 / Chapter 1.1.1 --- Problems with Synchronous Systems --- p.1-1 / Chapter 1.1.2 --- The Advantages of Self-timed Systems --- p.1-2 / Chapter 1.1.3 --- Self-Timed Cell Library --- p.1-3 / Chapter 1.2 --- Overview of the Thesis --- p.1-5 / Chapter CHAPTER2 --- BACKGROUND / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Models for Asynchronous System --- p.2-2 / Chapter 2.2.1 --- Huffman model --- p.2-2 / Chapter 2.2.2 --- Muller model --- p.2-4 / Chapter 2.3 --- Self-timed System --- p.2-5 / Chapter 2.3.1 --- Definitions and Assumptions --- p.2-6 / Chapter 2.4 --- Design Methodologies --- p.2-8 / Chapter 2.4.1 --- Differential Logic Structure Design Methodology --- p.2-9 / Chapter 2.4.1.1 --- Data Path --- p.2-9 / Chapter 2.4.1.2 --- Control Path --- p.2-10 / Chapter 2.4.2 --- Micropipeline Design Methodology --- p.2-12 / Chapter 2.4.2.1 --- Data Path --- p.2-12 / Chapter 2.4.2.2 --- Control Path --- p.2-13 / Chapter CHAPTER3 --- SELF-TIMED CELL LIBRARY / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Muller C element --- p.3-1 / Chapter 3.3 --- Differential Cascode Voltage Switch Logic Circuits --- p.3-6 / Chapter 3.3.1 --- INVERTER --- p.3-8 / Chapter 3.3.2 --- "AND, OR, NAND, NOR" --- p.3-8 / Chapter 3.3.3 --- "XOR, XNOR" --- p.3-10 / Chapter 3.4 --- Latches --- p.3-11 / Chapter 3.4.1 --- Precharged Latch --- p.3-12 / Chapter 3.4.2 --- Capture and Pass Latch --- p.3-12 / Chapter 3.5 --- Delay Elements --- p.3-13 / Chapter 3.6 --- Discussion --- p.3-15 / Chapter CHAPTER4 --- THE CHARACTERISTICS OF SELF-TIMED CELL LIBRARY / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- The Simulation Characteristics --- p.4-2 / Chapter 4.2.1 --- HSPICE program --- p.4-2 / Chapter 4.2.2 --- Characterization Information and Datasheet terms --- p.4-5 / Chapter 4.2.3 --- Characterization values --- p.4-6 / Chapter 4.3 --- The Experimental Analysis --- p.4-6 / Chapter 4.4 --- Experimental Result and Discussion --- p.4-9 / Chapter 4.4.1 --- Experimental Result --- p.4-9 / Chapter 4.4.2 --- Comparison of the characteristics of C-elements --- p.4-12 / Chapter 4.4.3 --- Comparison of simulation with experimental results --- p.4-13 / Chapter 4.4.4 --- Properties of DCVSL gate --- p.4-14 / Chapter 4.4.5 --- The Characteristics of Delay elements --- p.4-15 / Chapter 4.5 --- CAD Features on Cadence --- p.4-16 / Chapter CHAPTER5 --- DESIGN EXAMPLE: SELF-TIMED MATRIX MULTIPLIER / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- A Matrix Multiplier using DCVSL structure --- p.5-2 / Chapter 5.2.1 --- Structure --- p.5-2 / Chapter 5.2.2 --- Handshaking Control Circuit --- p.5-3 / Chapter 5.2.2.1 --- Handshaking Control Circuit of Pipeline --- p.5-4 / Chapter 5.2.2.2 --- Handshaking Control Circuit of Feedback Path --- p.5-8 / Chapter 5.3 --- A Matrix Multiplier using Micropipeline Structure --- p.5-10 / Chapter 5.3.1 --- Structure --- p.5-10 / Chapter 5.3.2 --- Control Circuit --- p.5-12 / Chapter 5.4 --- Experimental Result --- p.5-13 / Chapter 5.4.1 --- The Matrix Multiplier using DCVSL structure --- p.5-13 / Chapter 5.4.2 --- The Matrix Multiplier using Micropipeline structure --- p.5-16 / Chapter 5.5 --- Comparison of DCVSL structure and Micropipeline structure --- p.5-18 / Chapter CHAPTER6 --- CONCLUSION / Chapter 6.1 --- Achievement --- p.6-1 / Chapter 6.1.1 --- Self-timed Cell Library --- p.6-1 / Chapter 6.1.2 --- Self-timed System Design simplification --- p.6-2 / Chapter 6.1.3 --- Area and Speed --- p.6-3 / Chapter 6.1.4 --- Applications --- p.6-4 / Chapter 6.2 --- Future work --- p.6-6 / Chapter 6.2.1 --- Interface with synthesis tools --- p.6-6 / Chapter 6.2.2 --- Mixed Circuit Design --- p.6-6 / REFERENCES / APPENDICES