Lynne Michelle Brocco. / Orginally presented as author's thesis (M.S.--Massachusetts Institute of Technology), 1987. / "References": p. 92-94. / Supported by the U.S. Air Force grant AFOSR-86-0164

M.S. / Computer Science & Engineering / A Static Rule Checker for NMOS and CMOS VLSI Circuits is described. MOSSTAT makes a number of different static rule checks on a circuit. These checks help the user to detect and isolate errors such as improper network connectivity or invalid transistor sizes, and can be run interactively to allow for orderly execution each rule check. The results are stored in a data base. MOSSTAT provides a simple query language that allows the user to selectively retrieve this information from the data base. Transistors are classified according to their type and function. Logic gates are also classified according to their style. The results of these analyses are useful in isolating possible circuit design problems.

Ph.D. / Electrical Engineering / Nanometer-scale devices have attracted great attention as the ultimate evolution of silicon integrated circuit technology. However, fabrication of nanometer-scale silicon based devices has met great difficulty because it places severe constraints on process technology. This is especially true for SiGe/Si heterostructures because they are particularly sensitive to strain relaxation and/or process induced defects. Recently developed Pulsed Laser Induced Epitaxy (PLIE) offers a promising approach for the fabrication of nanometer- scale SiGe/Si devices. It possesses the advantage of ultra-short time, low thermal budget and full compatibility with current silicon technology. The selective nature of the process allows epitaxial growth of high quality, localized SiGe layers in silicon. In this thesis, a process to fabricate SiGe nanowires in silicon using PLIE is described. In particular, Ge nanowires with a cross-section of ~6 x 60 nm² are first formed using a lift-off process on the silicon substrate with e-beam lithography, followed by a thin low-temperature oxide deposition. Defect-free SiGe nanowires with a cross-section of ~25 x 95 nm² are then produced by impinging the laser beam on the sample. We thus demonstrate PLIE is a suitable fabrication technique for SiGe/Si nanostructures. Fabrication of Ge nanowires is also studied using Focused Ion Beam (FIB) micromachining techniques. Based on the SiGe nanowire process, we propose two advanced device structures, a quantum wire MOSFET and a lateral SiGe Heterojunction Bipolar Transistor (HBT). MEDICI simulation of the lateral SiGe HBT demonstrates high performance of the device. In order to characterize the SiGe nanowires using cross-sectional transmission electron microscopy, an advanced versatile focused ion beam assisted sample preparation technique using a multi-layer stack scheme for localized surface structures is developed and described in this thesis.

A series of complex digital blocks have been designed and fabricated using the newly developed current-mode differential CMOS logic family viz. the Folded Source-Coupled Logic ( FSCL ). The main feature of this logic family is the low current spikes generated during the switching transitions ( at least 2 orders of magnitude smaller than the conventional static CMOS gates ). The design of a decimation filter using novel Multi-Rate systolic architecture and it's implementation in Folded Source-Coupled Logic is also considered. The decimation filter thus designed can be used in mixed-mode applications like Sigma-Delta A/D converter to improve it's performance characteristics like dynamic range, resolution and phase linearity at higher sampling rates. / Graduation date: 1992

Fully efficient systolic arrays for the solution of Toeplitz matrices using Schur algorithm [1] have been obtained. By applying clustering mapping method [2], the complexity of the algorithm is 0(n) and it requires n/2 processing elements as opposed to n processing elements developed elsewhere [1]. The motivation of this thesis is to obtain efficient pipeline arrays by using the synthesis procedure to implement Toeplitz matrix solution. Furthermore, we will examine pipeline structures for the Toeplitz system factorization and back-substitution by obtaining clustering and Multi-Rate Array structures. These methods reduce the number of processing elements and enhance the computational speed. Comparison and advantage of these methods to other method will be presented. / Graduation date: 1992

New low power solutions for Very Large Scale Integration (VLSI) are proposed. Especially, we focus on leakage power reduction. Although neglected at 0.18u technology and above, leakage power is nearly equal to dynamic power consumption in nanoscale technology, e.g., 0.07u. We present a novel circuit structure, we call it sleepy stack, which is a combination of two well-known low-leakage techniques: the forced stack and sleep transistor techniques. Unlike the forced stack technique, the sleepy stack technique can utilize high-Vth transistors without incurring a large delay increase. Also, unlike the sleep transistor technique, the sleepy stack technique can retain exact logic state while achieving similar leakage power savings. In short, our sleepy stack structure achieves ultra-low leakage power consumption while retaining logic state. We apply the sleepy stack technique to both generic logic circuits as well as SRAM. At 0.07u technology, the sleepy stack logic circuits achieves up to 200X leakage reduction compared the forced stack technique with small (under 7%) delay variations and 51~118% area overheads. The sleepy stack SRAM cell with 1.5xVth achieves 5X leakage reduction with 32% delay increase or 2.49X leakage reduction without delay increase compared to the high-Vth SRAM cell. As such, the sleepy stack technique can be applicable to a design that requires ultra-low leakage power with quick response time while paying area and delay cost. We also propose a new low power architectural technique named Low-Power Pipelined Cache (LPPC). Although a conventional pipelined cache is mainly used to reduce cache access time, we lower supply voltage of cache using LPPC to save dynamic power. We achieve 20.43% processor dynamic energy savings with 4.14% execution cycle increase using 2-stage low-Vdd LPPC. Furthermore, we apply LPPC to the sleepy stack SRAM. The sleepy stack pipelined SRAM achieves 17X leakage power reduction while increasing execution time by 4% on average. Although this combined technique increases active power consumption by 33%, this technique is well suited for the system that spends most of its time in sleep mode.

The unabated silicon technology scaling makes design and manufacturing increasingly harder in nanometer VLSI. Emerging technologies on the horizon require strong design automation to handle the large complexity of future systems. This dissertation studies eight related research topics in design and manufacturing closure in nanometer VLSI as well as design optimization for emerging technologies from physical synthesis perspective. In physical synthesis for design closure, we study three research topics, which are key challenges in nanometer VLSI designs: (a) We propose a highly efficient floorplanning algorithm to minimize substrate noise for mixed-signal system-on-a-chip designs. (b) We propose a clock tree synthesis algorithm to reduce clock skew under thermal variation. (c) We develop a global router, BoxRouter to enhance routability which is one of the classic but still critical challenges in modern VLSI. In physical synthesis for manufacturing closure, we propose the first systematic manufacturability aware routing framework to address three key manufacturing challenges: (a) We develop a predictive chemical-mechanical polishing model to guide global routing in order to reduce surface topography variation. (b) We formulate a random defect minimize problem in track routing, and develop a highly efficient algorithm. (b) We propose a lithography enhancement technique during detailed routing based on statistical and macro-level Post-OPC printability prediction. Regarding design optimization of emerging technologies, we focus on two topics, one in double patterning technology for future VLSI fabrication and the other in microfluidics for biochips: (a) We claim double patterning should be considered during physical synthesis, and propose an effective double patterning technology aware detailed routing algorithm. (b) We propose a droplet routing algorithm to improve routability in digital microfluidic biochip design. / text

In the sub-65nm VLSI technology, the variation effects like manufacturing variation, power supply noise and temperature variation become very significant. As one of the most vital components in any synchronous VLSI chip, the Clock Distribution Network (CDN) is especially sensitive to these variations. The unwanted clock skews caused by the variation effects consume increasing proportion of the clock cycle, thereby limiting chip performance and yield. Thus, making the clock network variation-tolerant is a key objective in the chip designs of today. In this dissertation, we propose several techniques that can be used to synthesize variation-tolerant clock networks. Our contributions can be broadly classified into following four categories: (i) Efficient algorithms for synthesizing link based non-tree clock networks. (ii) A methodology for synthesizing a balanced, variation tolerant, buffered clock network with cross-links. (iii) A comprehensive framework for planning, synthesis and optimization of clock mesh networks. (iv) A chip-level clock tree synthesis technique to address issues unique to hierarchical System-On-a-Chip (SOC) designs that are becoming more and more frequent today. Depending on the performance requirements and resource constraints of a given chip, the above techniques can be used separately or in combination to synthesize a variation tolerant clock network. / text

The Best MPhil Thesis in the Faculties of Dentistry, Engineering, Medicine and Science (University of Hong Kong), Li Ka Shing Prize,2009-2010 / published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy