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The Global ETD Search service is a free service for researchers
to find electronic theses and dissertations. This service is
provided by the
Networked Digital Library of Theses and Dissertations.
Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
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Showing 151 to 160 of 217 (0.105 seconds)Spelling suggestions: "subject:"entegrated circuits very large scale"" "subject:"entegrated circuits nery large scale""
| 151 |
VLSI systems simulation / Michael T. PopePope, Michael T. (Michael Travers) January 1991 (has links)
Bibliography: leaves 255-280 / viii, 280 leaves : ill ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1992
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| 152 |
Limitations and opportunities for wire length prediction in gigascale integrationAnbalagan, Pranav. January 2007 (has links)
Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007. / Committee Chair: Dr. Jeff Davis; Committee Member: Dr. James D. Meindl; Committee Member: Dr. Paul Kohl; Committee Member: Dr. Scott Wills; Committee Member: Dr. Sung Kyu Lim.
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| 153 |
Algorithm and Hardware Co-Design for Local/Edge ComputingJiang, Zhewei January 2020 (has links)
Advances in VLSI manufacturing and design technology over the decades have created many computing paradigms for disparate computing needs. With concerns for transmission cost, security, latency of centralized computing, edge/local computing are increasingly prevalent in the faster growing sectors like Internet-of-Things (IoT) and other sectors that require energy/connectivity autonomous systems such as biomedical and industrial applications.
Energy and power efficient are the main design constraints in local and edge computing. While there exists a wide range of low power design techniques, they are often underutilized in custom circuit designs as the algorithms are developed independent of the hardware. Such compartmentalized design approach fails to take advantage of the many compatible algorithmic and hardware techniques that can improve the efficiency of the entire system. Algorithm hardware co-design is to explore the design space with whole stack awareness.
The main goal of the algorithm hardware co-design methodology is the enablement and improvement of small form factor edge and local VLSI systems operating under strict constraints of area and energy efficiency. This thesis presents selected works of application specific digital and mixed-signal integrated circuit designs. The application space ranges from implantable biomedical devices to edge machine learning acceleration.
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| 154 |
Time domain space mapping optimization of digital interconnect circuitsHaddadin, Baker. January 2009 (has links)
No description available.
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| 155 |
Single layer routing : mapping topological to geometric solutionsHong, Won-kook. January 1986 (has links)
No description available.
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| 156 |
Area efficient PLA's for the recognition of regular expression languagesChandrasekhar, Muthyala. January 1985 (has links)
No description available.
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| 157 |
Model order reduction for efficient modeling and simulation of interconnect networksMa, Min January 2007 (has links)
No description available.
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| 158 |
Test vector generation and compaction for easily testable PLAsDraier, Benny. January 1988 (has links)
No description available.
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| 159 |
Design of a VLSI convolver for a robot vision systemBoudreault, Yves, 1959- January 1986 (has links)
No description available.
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| 160 |
A MOS switch-level simulator with delay calculation /Khordoc, Karim January 1986 (has links)
No description available.
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