In this thesis, several techniques for the test generation of VHDL behavioral models are proposed. An algorithm called HBTG, Hierarchical Behavioral Test Generator, is developed and implemented to systematically generate tests for VHDL behavioral models. HBTG accepts the Process Model Graph and the precomputed tests for the individual processes of the model from which it constructs a test sequence that exercises the model hierarchically. The construction of the test sequence is automatic if the tests for the individual processes of the model are provided. The test sequence derived can be used for the simulation of the model. By comparing the simulation outputs with the data sheet or the design specifications of the corresponding circuit, a user can tell if the functionality of the model is as expected or any functional faults exist. Simulation results and conclusions are given. Some suggestions for further improvements of the program are discussed. / Master of Science

This thesis describes the development of BACKANN, a tool for the back annotation of timing delays into VHDL models. BACKANN uses the Process Model Graph and the VHDL behavioral model generated by the Modeler's Assistant as the base for backannotation. BACKANN determines the delay values that are required for the signal assignments in the behavioral model. It generates a gate-level design of the model using the Synopsys Design Compiler. It extracts the values for the delays required from the gate-level design. It then back-annotates these values into the VHDL behavioral model. BACKANN is thus a design automation tool that helps the development of VHDL behavioral models with realistic timing and thus quickens the design cycle. / Master of Science

The author begins with a short introduction to current neural network practices and pitfalls including an in depth discussion of the meaning behind the equations. Specifically, a description of the underlying processes involved is given which likens training to the biological process of cell differentiation. Building on these ideas, an improved method of generating integer based binary neural networks is developed. This type of network is particularly useful for the optical character recognition problem, but methods for usage in the more general case are discussed. The new method does not use training as such. Rather, the training data is analyzed to determine the statistically significant relationships therein. These relationships are used to generate a neural network structure that is an idealization of the trained version in that it can accurately extrapolate from existing knowledge by exploiting known relationships in the training data. The paper then turns to the design and testing of a VLSI CMOS chip which was created to utilize the new technique. The chip is based on the MOSIS 2Jlm process using a 2200A x 2200A die that was shaped into a special purpose microprocessor that could be used in any of a number of pattern recognition applications with low power requirements and/or limiting considerations. Simulation results of the methods are then given in which it is shown that error rates of less than 5% for inputs containing up to 30% noise can easily be achieved. Finally, the thesis concludes with ideas on how the various methods described might be improved further. / Master of Science

This thesis describes the development of the Process Test Generation (PTG) software for the testing of single-process VHDL behavioral models. The PTG software, along with Hierarchical Behavioral Test Generator (HBTG) and Modeler's Assistant, forms a part of the Automatic Test Generation System being developed at Virginia Tech. The PTG software transforms the VHDL description of a circuit, given by Modeler's Assistant, into a Control Flow Graph (CFG) that describes the control and data flow information in the behavioral model. The process test generation algorithm, called the PTG algorithm, uses the CFG to generate stimulus/response test sets that test all the functions of the VHDL model. The algorithm creates events on signals, propagates these events and uses simulation to obtain responses. Various features present in the software like the generation of the Control Flow Graph, the PTG algorithm, and the construction of paths through the CFG to propagate and justify events, are discussed. The test sets generated by PTG can be used for the hierarchical test generation by HBTG, which was developed earlier. Another program, called Test Bench Generator (TBG), is presented in this thesis. It is used to convert the test sequence generated by HBTG into a VHDL Test Bench that can be used for simulation. / Master of Science

Today digital signal processing techniques are employed in a variety of applications. Two factors contributing to the growth in the use of digital signal processing (DSP) are the advent of custom VLSI that has made using digital signal processing techniques to solve real time problems more attractive and powerful; and the ease and flexibility of application of digital signal processing technique both in hardware and software. The purpose of this paper is to present the design of a digital signal processor chip based on a consideration of VLSI technology and signal processing requirement for radar applications. The paper reviews basic signal processing tasks , giving emphasis to the digital filters and spectral analysis which are generally the required functions in radar signal processing. That leads to the discussion of two DSP algorithms Discret Fourier Transform and Fast Fourier Transform. The basic hardware components required are described along with the software to implement the DSP algorithms. Finally, an example demonstrates the use of processor chip to perform transversal filter function.

BIDES (A BIST Design Expert System) is an expert system for incorporating BIST into a digital circuit described with VHDL. BIDES modifies a circuit to produce a self-testable circuit by inserting BIST hardware such as pseudorandom pattern generators and signature analysis registers. In inserting BIST hardware, BIDES not only makes a circuit self-testable, but also incorporates the appropriate type of BIST structure so that a set of user-specified constraints on hardware overhead and testing time can be satisfied. This flexibility comes from the formulation of the BIST design problem as a search problem. A satisfactory BIST structure is explored through an iterative process of evaluation and regeneration of BIST structure. The process of regeneration is performed by a problem solving technique called hierarchical planning. In order to apply a hierarchical planning technique, we introduce an abstraction hierarchy in BIST design. Using the abstraction hierarchy, the knowledge of the BIST design process is represented with several operators defined on the abstraction levels. This type of knowledge representation in conjunction with hierarchical planning led to an easy implementation of the system and results in an easily modifiable system. In this dissertation, we also study a BIST scheme called cascade testing. ln cascade testing, a signature analysis register is used concurrently as a test pattern generator in order to reduce the overall testing time by improving testing parallelism. The characteristics of the patterns generated by the signature analysis register are investigated through analysis as well as experiments. lt is shown that the patterns generated by signature analysis registers are rarely repeated when the number of patterns generated is relatively small compared to the number of all possible patterns. It is also shown that the patterns generated by signature analysis registers are almost random. Therefore, signature analysis registers can be used effectively as pseudorandom pattern generators. The practicality of cascade testing is investigated by fault simulation experiments using an example circuit. / Ph. D.

Power dissipation of integrated circuits is the most demanding issue for very large scale integration (VLSI) design engineers, especially for portable and mobile applications. Use of multiple supply voltages systems, which employs level converter between two voltage islands is one of the most effective ways to reduce power consumption. In this thesis work, a unique level converter known as universal level converter (ULC), capable of four distinct level converting operations, is proposed. The schematic and layout of ULC are built and simulated using CADENCE. The ULC is characterized by performing three analysis such as parametric, power, and load analysis which prove that the design has an average power consumption reduction of about 85-97% and capable of producing stable output at low voltages like 0.45V even under varying load conditions.

Continuing advances with VLSI have enabled engineers to build high performance computer systems to solve complex problems. The real-world problems and tasks like pattern recognition, speech recognition, etc. still remain elusive to the most advanced computer systems today. Many advances in the science of computer design and technology are coming together to enable the creation of the next-generation computing machines to solve real-world problems, which the human brain does with ease. One such engineering advance is the field of neuromorphic engineering, which tries to establish closer links to biology and help us investigate the problem of designing better computing machines. A chip built with the principles of neuromorphic engineering is called as neuromorphic chip. Neuromorphic chip aims to solve real-world problems. As the complexity of the problem increases, the computation capability of these chips can become a limitation. In order to improve the performance and accomplish a complex task in the real-world, many such chips need to be integrated into a system. Hence, efficiency of such a system depends on effective inter-chip communication. Here, the work presented aims at building a message-passing network (Digital Fabric) simulator, that integrates many such chips. Each chip represents a binary event-based unit called spiking analog cortical module. The inter-chip communication protocol employed here is called as Address Event Representation. Here, the Digital Fabric is built in three revisions, with different architectures being considered in each revision. The complexity is increased at each iteration stage. The experiments performed in each revision test the performance of such configuration systems and results proves to lay a foundation for further studies. In the future, building a high level simulation model will assist in scaling and evaluating various network topologies.

A model is presented which incorporates the advantages of a mixed mode simulation to characterize transmission line behavior in multiple coupled Transmission line systems. The model is intended for use by digital circuit designers who wish to be able to obtain accurate transmission line behavior for complex digital systems for which continuous time simulation tools such as SPICE would time prohibitive. The model uses a transverse electromagnetic wave approximation to obtain solutions to the basic transmission line equations. A modal analysis technique is used to solve for the attenuation and propagation constants for the transmission lines. Modal analysis done in the frequency domain after a Fast Fourier Transform of the time-domain input signals. Boundary conditions are obtained from the Thevinized transmission line input equivalent circuit and the transmission line output load impedance. The model uses a unique solution queue system that allows n-line coupled transmission lines to be solved without resorting to large order matrix methods or the need to diagonals larger matrices using linear transformations. This solution queue system is based on the method of solution superposition. As a result, the CPU time required for the model is primarily a function of the number of transitions and not the number of lines modeled. Incorporation of the model into event driven circuit simulators such as Network C is discussed. It will be shown that the solution queue methods used in this model make it ideally suited for incorporation into a event-driven simulation network. The model presented in this thesis can be scaled to incorporate direct electromagnetic coupling between first, second, or third lines adjacent to the line transitioning. It is shown that modeling strictly adjacent line coupling is adequate for typical digital technologies. It is shown that the model accurately reproduces the transmission line behavior of systems modeled by previous authors. Example transitions on a 8-line system are reviewed. Finally, future model improvements are discussed.

This work presents a new energy saving technique for modern digital designs. We propose Time Interleaved Multi-Rail (TIMR) - a method for providing two dynamic supply rails to a circuit. This technique uses the first supply rail to mask the transition delay while changing the voltage of the second rail. We examine the design of TIMR as well as the implementation and considerations. We propose a number of control schemes that range from traditional DVFS to "race to sleep". This thesis also shows simulations of the technique using a existing voltage regulator in order to find the time and energy overhead of implementing the design. We find a 100μs switching time delay and 118μJ energy overhead associated with changing the voltage rail. This work concludes with comparisons to current energy saving techniques. / Graduation date: 2012