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In this master thesis work, the power dissipation in a current-steering digital- to-analog converter, DAC, has been studied. The digital as well as the analog power dissipation have been modelled in MATLAB and it is shown that the MATLAB models agrees well with simulation results from the circuit simulator (Spectre). A case study on a DAC designed at Ericsson Microelectronics AB in Linköping has also been done. The DAC is a thermometer-coded current-steering DAC suitable for telecommunications applications. The telecommunication standards that have been studied are asymmetric digital subscriber line, ADSL, very high speed data digital subscriber line, VDSL, and, wireless local area network, WLAN. The conlusion of the study is that the power dissipation of the specific DAC, used in ADSL applications, 75mW, is far from optimized. It can theoretically be lowered to 3.5mW.

<p>In this master thesis work, the power dissipation in a current-steering digital- to-analog converter, DAC, has been studied. The digital as well as the analog power dissipation have been modelled in MATLAB and it is shown that the MATLAB models agrees well with simulation results from the circuit simulator (Spectre). </p><p>A case study on a DAC designed at Ericsson Microelectronics AB in Linköping has also been done. The DAC is a thermometer-coded current-steering DAC suitable for telecommunications applications. The telecommunication standards that have been studied are asymmetric digital subscriber line, ADSL, very high speed data digital subscriber line, VDSL, and, wireless local area network, WLAN. The conlusion of the study is that the power dissipation of the specific DAC, used in ADSL applications, 75mW, is far from optimized. It can theoretically be lowered to 3.5mW.</p>

A rake receiver, which resolves multipath signals corrupted by a fading channel, is the most complex and power consuming block of a modem chip. Therefore, it is essential to design a rake receiver be efficient in hardware and power. We investigated a design of a rake receiver for the WCDMA (Wideband Code Division Multiple Access) system, which is a third generation wireless communication system. Our rake receiver design is targeted for mobile units, in which low-power consumption is highly important. We made judicious judgments throughout our design process to reduce the overall circuit complexity by trading with the performance. The reduction of the circuit complexity results in low power dissipation for our rake receiver. As the first step in the design of a rake receiver, we generated a software prototype in MATLAB. The prototype included a transmitter and a multipath Rayleigh fading channel, as well as a rake receiver with four fingers. Using the software prototype, we verified the functionality of all blocks of our rake receiver, estimated the performance in terms of bit error rate, and investigated trade-offs between hardware complexity and performance. After the verification and design trade-offs were completed, we manually developed a rake receiver at the RT (Register Transfer) level in VHDL. We proposed and incorporated several schemes in the RT level design to enhance the performance of our rake receiver. As the final step, the RT level design was synthesized to gate level circuits targeting TSMC 0.18 mm CMOS technology under the supply voltage of 1.8 V. We estimated the performance of our rake receiver in area and power dissipation. Our experimental results indicate that the total power dissipation for our rake receiver is 56 mW and the equivalent NAND2 circuit complexity is 983,482. We believe that the performance of our rake receiver is quite satisfactory. / Master of Science

In 2012, plasma figuring was proven to be an alternative solution for the fabrication of large scale ultra-precise optical surfaces. Indeed, plasma figuring was successfully demonstrated on a metre class glass surface. The process was exceptionally rapid but residual errors were observed. This thesis addresses this issue by proposing an enhanced tool that provides a highly collimated plasma jet. The enhanced tool is characterized by a targeted material removal footprint in the range 1 to 5 mm FWHM. The energy beam is provided by an Inductively Coupled Plasma (ICP) torch equipped with a De-Laval nozzle. This thesis focuses on characterization and optimisation of the bespoke plasma torch and its plasma jet. Two research investigations were carried out using both numerical and experimental approaches. A novel CFD model was created to analyse and understand the behaviour of high temperature gas in the De-Laval nozzle. The numerical approach, that was based on appropriate profiles of temperature and velocity applied to the nozzle inlet, led to a significant reduction of computational resources. This model enabled to investigate the aerodynamic phenomena observed from the nozzle inlet up to the processed surface. Design rules and the effect of changing nozzle parameters were identified. Sensitivity analysis highlighted that the throat diameter is the most critical parameter. A challenging power dissipation analysis of the plasma torch was carried out. Temperature and flow rate in key components of the torch were measured. Experimental results enabled to calculate the power dissipation values for RF power up to 800 W and for the entire series of designed nozzles. This work enabled to scientifically understand the power dissipation mechanism in the bespoke ICP torches. In addition, by comparing the intensity of the power dissipation values, one nozzle was clearly identified as being more capable to provide a highly efficient plasma jet.

We present an energy conscious location-aware computing system that provides relevant information about the users current location. The location-aware computing system is initialized with a map (in the form of a graph) as well as audio files associated with several locations in the map. The system consists of: GPS receiver module, Serial port, Compact flash module, Stereo codec, Power manager module implementing three sub modules namely, GPS-to-real-world position conversion module (implements algorithm to convert GPS co-ordinates to graph nodes), Nearest-location-search module (implements modified Dijkstras algorithm), and User speed estimation module. The location-aware computing system receives the GPS co-ordinates for the current location from GPS receiver through the serial port. The system converts the GPS co-ordinates to map co-ordinates stored in the Compact Flash card. If the current location matches the landmarks of interest in the site, then the relevant audio details of the current location is played out to the user. The power manager sets the GPS co-ordinates update frequency to avoid keeping the system component on throughout the entire course of travel. The power manager implements an algorithm that works as follows: at any given location, the algorithm predicts the user speed by exponential average approach. The attenuation factor of this approach can be varied to account for the user speed history. The estimated speed is used to predict the time (say T) required to reach the next nearest location determined by Nearest-location-search module implementing modified Dijkstras algorithm. The subsystems are shut-down or switched to low-power mode for time T. After time T, the system will wake up and re-execute the algorithm.

<p>0.18 um CMOS technology is increasingly used in design and implementation of full adder cells. Hence, there is a need for better understanding of the effects of different cell designs on cell performance, including power dissipation and time delays. </p><p>This thesis contributes to better understanding of the behavior of single-bit full adder cells when low power-delay products are essential. Thirty one single-bit full adder cells have been implemented in Cadence tool suit and simulated using 0.18 µm CMOS technology to obtain a comprehensive study of the performance of the cells with respect to time (time-delays) and power consumption (power dissipation). </p><p>Simulation method used for performance measurements has been carefully devised to achieve as accurate measurements as possible with respect to time delay and power dissipation. The method combines the simple measurement technique for obtaining accurate time-delays and power dissipation of a cell, and the transistor resizing technique that allows systematicallyresizing of transistors to achieve minimal power-delay product. The original technique of sizing of the transistors has been extended in this thesis for the purpose of the performance measurements to include both resizing the transistors in the critical path and resizing the transistors on the global level, and therefore efficiently obtain minimal power-delay product for every cell. </p><p>The result of this performance study is an extensive knowledge of full adder cell behaviour with respect to time and power, including the limitations of the 0.18 µm CMOS technology when used in the area of full adder cells. Furthermore, the study identified full adder cell designs that demonstrated the best performance results with respect to power-delay products. </p><p>In general, the complex performance simulation method in this thesis that combines the simulation of time delay and critical path transistor resizing provides the most accurate measurements and as such can be used in the future performance analysis of single-bit full adder cells.</p>

0.18 um CMOS technology is increasingly used in design and implementation of full adder cells. Hence, there is a need for better understanding of the effects of different cell designs on cell performance, including power dissipation and time delays. This thesis contributes to better understanding of the behavior of single-bit full adder cells when low power-delay products are essential. Thirty one single-bit full adder cells have been implemented in Cadence tool suit and simulated using 0.18 µm CMOS technology to obtain a comprehensive study of the performance of the cells with respect to time (time-delays) and power consumption (power dissipation). Simulation method used for performance measurements has been carefully devised to achieve as accurate measurements as possible with respect to time delay and power dissipation. The method combines the simple measurement technique for obtaining accurate time-delays and power dissipation of a cell, and the transistor resizing technique that allows systematicallyresizing of transistors to achieve minimal power-delay product. The original technique of sizing of the transistors has been extended in this thesis for the purpose of the performance measurements to include both resizing the transistors in the critical path and resizing the transistors on the global level, and therefore efficiently obtain minimal power-delay product for every cell. The result of this performance study is an extensive knowledge of full adder cell behaviour with respect to time and power, including the limitations of the 0.18 µm CMOS technology when used in the area of full adder cells. Furthermore, the study identified full adder cell designs that demonstrated the best performance results with respect to power-delay products. In general, the complex performance simulation method in this thesis that combines the simulation of time delay and critical path transistor resizing provides the most accurate measurements and as such can be used in the future performance analysis of single-bit full adder cells.

For the application of 4G wireless communication system, this thesis aims to develop a high-quality-factor and low-power-dissipation suspending micro-inductor using electrochemical deposition and surface micromachining technologies. This research presents three technical points to improve the quality factor and reduce the power dissipation of micro inductor, including (i) to adopt a low resistivity material (copper) as the conducting layer to decrease the Eddy current due to the skin effect and reduce the total series resistance and energy loss, (ii) to utilize a suspending structure to diminish the power loss through the substrate and (iii) to replace the silicon wafer with a high resistance substrate (Corning 7740) to compress effectively the power dissipation in high frequency operation. The implemented suspending micro-inductors were characterized by a commercial network analyzer (Agilent E5071C) under 0.5~20 GHz testing frequency range. All the inductances and quality factors of the micro-inductors proposed in this thesis are extracted by the Agilent ADS software. The optimized value of the quality factor is around to 24.9 and the corresponding inductance is equal to 5.43 nH .