The ability of radiation to cause transient faults in space borne as well as ground based computers is well known. with the density of VLSI circuits increasing every year, the probability of an upset by radiation is becoming more likely. However, research in this area has matured over the last decade, and the mechanisms which cause such faults are better understood. This understanding enables us to propose ideas to eliminate or lessen the effects of radiation on VLSI circuits. Most of the research to date has concentrated on the effect of transient faults on flip-flops rather than combinational logic. This is due to several reasons. First, transient faults, also known as Single Event Upsets (SEU), were first observed in memory circuits located on board satellites. Second, an SEU can leave a lasting effect on a circuit if it occurs in a flip-flop, and third, SEUs can cause the output of a flip-flop to change state more easily if it occurs directly in the flip-flop rather than in the combinational logic. In combinational logic, the node struck by the radiation is completely disjoint from the flip-flops output node. This in effect causes the SEU to satisfy more criteria in order to change the flip-flops output state. The criteria that the SEU must satisfy tend to be complex, and this complexity has caused many researchers to believe that SEUs that occur in combinational logic cause negligible errors in the state of flip-flops. Thus, in this thesis, the criteria for latching a SEU are discussed, and original methods are presented that can be used to determine the probability of an SEU occurring at any node in a circuit will cause a change in the output state of a flip-flop. The methods are then incorporated into a program, named SUPER II, that is able to evaluate the circuit to determine the nodes with the highest probability of having a SEU error latched. The results from the program show that SEUs that occur in combinational logic can have a significant probability of becoming latched. / Master of Science

Modeling is an essential step in the design of digital circuits [71. The coding of behavioral models for complex devices is a labor intensive task. Even with the use of a to01like the "Modeler's Assistant" [4}, the development of behavioral models is time consuming and labor intensive. The use of re-usable code along with a tool like the Modeler's Assistant can speed up model development. This thesis defines a set of higher level primitives which can be used for this purpose. These primitives are built as a macro library into the tool. The Modeler's Assistant together with the modeling primitives provides us with a tool that can simplify the process of model development. / Master of Science

No description available.

Real-time image processing involves processing a wide spectrum of algorithms on huge data sets. Processing at the pixel data rate demands more powerful parallel machines than those developed for conventional image processing. This research takes advantage of current VLSI technology to examine a new approach for processing arbitrary algorithms at real-time data rate. It is based on embedding the algorithms, expressed by their dependency graphs, into two dimensional regularly connected processing arrays. Each node in a graph represents an operation which can be processed by an individual processor in the array. The embedding is performed such that data can be processed in a pipeline fashion as they are received. The result is a machine which exploits functional parallelism and data pipelining simultaneously. The presentation is divided into three parts: the first discusses graphical representation for general image processing algorithms, taking into account the nature of the data flow in real-time systems. The conditions for pipelining the processing of the graph are derived. Next the logical design of a class of VLSI arrays is considered. These arrays can be configured to embed arbitrary problem graphs. The discussion involves the architecture of the array, the architecture of its processing elements and an efficient programming scheme. Finally, static embedding of the dependency graphs into the proposed array is considered. Lower and upper bounds on the area needed to embed any graph are found. Three heuristic procedures to embed the graph at minimum cost are developed, implemented and tested. / Ph. D. / incomplete_metadata

Partial scan has served as an alternative solution for test generation for sequential circuits. As only a portion of flip-flops are incorporated into a scan chain in partial scan design, scan flip-flop selection constitutes a key procedure in partial scan. In this thesis, we propose a new way of selecting scan flip-flops, the Extended Tracking Algorithm (ETA). ETA is a test generation based method and aims to find the conditions that can lead to the detection of as many aborted faults as possible. The faults aborted by a sequential automatic test pattern generator (ATPG) are targeted in ETA and the requirements for the detection of the faults are used for the selection of scan flip-flops. The Extended Tracking Algorithm is realized in two different algorithms, optimal and heuristic, depending on the objectives. The optimal algorithm guarantees the minimal set of flip-flops for the detection of all of the aborted faults in a given circuit, but it has exponential worst case complexity. The heuristic algorithm, on the other hand, obtains a near optimal solution in shorter time. ETA provides a spectrum of accurate fault efficiency and/or fault coverage so that the designer can choose an affordable option. The method is simple and compatible with other scan flip-flop selection approaches. We implemented the Extended Tracking Algorithm in a program called BELLONA. Experiments have been conducted on ISCAS89 benchmark circuits with different specifications. Our experimental results show that ETA is an efficient solution for partial scan deign and only a small portion of scan flip-flops are necessary to obtain extremely high fault efficiency. / M.S.

Memory design is a crucial component of VLSI system design from area, power and performance perspectives. To meet the increasingly challenging system specifications, architecture, circuit and device level innovations are required for existing memory technologies. Emerging memory solutions are widely explored to cater to strict budgets. This thesis presents design methodologies for custom memory design with the objective of power-performance benefits across specific applications. Taking example of STTRAM (spin transfer torque random access memory) as an emerging memory candidate, the design space is explored to find optimal energy design solution. A thorough thermal reliability study is performed to estimate detection reliability challenges and circuit solutions are proposed to ensure reliable operation. Adoption of the application-specific optimal energy solution is shown to yield considerable energy benefits in a read-heavy application called MBC (memory based computing). Circuit level customizations are studied for the volatile SRAM (static random access memory) memory, which will provide improved energy-delay product (EDP) for the same MBC application. Memory design has to be aware of upcoming challenges from not only the application nature but also from the packaging front. Taking 3D die-folding as an example, SRAM performance shift under die-folding is illustrated. Overall the thesis demonstrates how knowledge of the system and packaging can help in achieving power efficient and high performance memory design.

The Programmable Logic Array (PLA) has been widely used in the design of VLSI circuits and systems because of its regularity, flexibility, and simplicity. The equivalence problem is typically to verify that the final description of a circuit is functionally equivalent to its initial description. Verifying the functional equivalence of two descriptions is equivalent to proving their logical equivalence. This problem of pure logic is essential to circuit design. The most widely used technique to solve the problem is based on Binary Decision Diagram or BDD, proposed by Bryant in 1986. Unfortunately, BDD requires too much time and space to represent moderately large circuits for equivalence testing. We design and implement a new algorithm called the Cover-Merge Algorithm for the equivalence problem based on a divide-and-conquer strategy using the concept of cover and a derivational method. We prove that the algorithm is sound and complete. Because of the NP-completeness of the problem, we emphasize simplifications to reduce the search space or to avoid redundant computations. Simplification techniques are incorporated into the algorithm as an essential part to speed up the the derivation process. Two different sets of heuristics are developed for two opposite goals: one for the proof of equivalence and the other for its disproof. Experiments on a large scale of data have shown that big speed-ups can be achieved by prioritizing the heuristics and by choosing the most favorable one at each iteration of the Algorithm. Results are compared with those for BDD on standard benchmark problems as well as on random PLAs to perform an unbiased way of testing algorithms. It has been shown that the Cover-Merge Algorithm outperforms BDD in nearly all problem instances in terms of time and space. The algorithm has demonstrated fairly stabilized and practical performances especially for big PLAs under a wide range of conditions, while BDD shows poor performance because of its memory greedy representation scheme without adequate simplification.

by Cheng King Sum Frankie. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaf 53). / Acknowledgments --- p.iv / List of Figures --- p.vii / List of Tables --- p.ix / Abstract --- p.x / Chapter Chapter1 --- Introduction --- p.1 / Chapter 1.1 --- Multiple Clock System --- p.1 / Chapter 1.2 --- Clock Multiplier --- p.2 / Phase-Locked Loop --- p.2 / Delay Locked Loop --- p.3 / Chapter 1.3 --- Objective --- p.5 / Chapter Chapter2 --- All-Digital Clock Multiplier --- p.6 / Chapter 2.1 --- Architecture --- p.6 / Chapter 2.2 --- Operation --- p.7 / Chapter 2.3 --- Implementation --- p.9 / Control Circuit --- p.9 / Phase-Locked Circuit --- p.11 / Frequency Detector --- p.12 / Frequency Divider --- p.13 / Synchronize Logic --- p.14 / DCO Control --- p.15 / Chapter Chapter3 --- Digitally-Controlled Oscillator --- p.16 / Chapter 3.1 --- Principle --- p.16 / Chapter 3.2 --- Design --- p.18 / Transient Analysis --- p.18 / Simulation result --- p.26 / Chapter 3.3 --- Layout --- p.30 / Chapter 3.4 --- Summary --- p.32 / Chapter Chapter4 --- Test and Measurement --- p.34 / Chapter 4.1 --- Digitally-Controlled Oscillator Characteristics --- p.34 / Chapter 4.2 --- All-Digital Clock Multiplier Characteristics --- p.43 / Chapter Chapter5 --- Conclusions --- p.51 / Chapter 5.1 --- Summary --- p.51 / Chapter 5.2 --- Recommendation for Future Work --- p.52 / References --- p.53 / Appendix A --- p.54 / Publications and Presentations --- p.54

by Johnson, Tin-Chak Pang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references. / Acknowledgments / Abstract / List of figures / List of tables / Chapter 1. --- Introduction --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Introduction to asynchronous system --- p.1-5 / Chapter 1.2.1 --- Motivation --- p.1-5 / Chapter 1.2.2 --- Hazards --- p.1-7 / Chapter 1.2.3 --- Classes of Asynchronous circuits --- p.1-8 / Chapter 1.3 --- Introduction to Transform Coding --- p.1-9 / Chapter 1.4 --- Organization of the Thesis --- p.1-16 / Chapter 2. --- Asynchronous Design Methodologies --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Self-timed system --- p.2-2 / Chapter 2.3 --- DCVSL Methodology --- p.2-4 / Chapter 2.3.1 --- DCVSL gate --- p.2-5 / Chapter 2.3.2 --- Handshake Control --- p.2-7 / Chapter 2.4 --- Micropipeline Methodology --- p.2-11 / Chapter 2.4.1 --- Summary of previous design --- p.2-12 / Chapter 2.4.2 --- New Micropipeline structure and improvements --- p.2-17 / Chapter 2.4.2.1 --- Asymmetrical delay --- p.2-20 / Chapter 2.4.2.2 --- Variable Delay and Delay Value Selection --- p.2-22 / Chapter 2.5 --- Comparison between DCVSL and Micropipeline --- p.2-25 / Chapter 3. --- Self-timed Multipliers --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Design Example 1 : Bit-serial matrix multiplier --- p.3-3 / Chapter 3.2.1 --- DCVSL design --- p.3-4 / Chapter 3.2.2 --- Micropipeline design --- p.3-4 / Chapter 3.2.3 --- The first test chip --- p.3-5 / Chapter 3.2.4 --- Second test chip --- p.3-7 / Chapter 3.3 --- Design Example 2 - Modified Booth's Multiplier --- p.3-9 / Chapter 3.3.1 --- Circuit Design --- p.3-10 / Chapter 3.3.2 --- Simulation result --- p.3-12 / Chapter 3.3.3 --- The third test chip --- p.3-14 / Chapter 4. --- Current-Sensing Completion Detection --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- Current-sensor --- p.4-2 / Chapter 4.2.1 --- Constant current source --- p.4-2 / Chapter 4.2.2 --- Current mirror --- p.4-4 / Chapter 4.2.3 --- Current comparator --- p.4-5 / Chapter 4.3 --- Self-timed logic using CSCD --- p.4-9 / Chapter 4.4 --- CSCD test chips and testing results --- p.4-10 / Chapter 4.4.1 --- Test result --- p.4-11 / Chapter 5. --- Self-timed ICT processor architecture --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Comparison of different architecture --- p.5-3 / Chapter 5.2.1 --- General purpose Digital Signal Processor --- p.5-5 / Chapter 5.2.1.1 --- Hardware and speed estimation : --- p.5-6 / Chapter 5.2.2 --- Micropipeline without fast algorithm --- p.5-7 / Chapter 5.2.2.1 --- Hardware and speed estimation : --- p.5-8 / Chapter 5.2.3 --- Micropipeline with fast algorithm (I) --- p.5-8 / Chapter 5.2.3.1 --- Hardware and speed estimation : --- p.5-9 / Chapter 5.2.4 --- Micropipeline with fast algorithm (II) --- p.5-10 / Chapter 5.2.4.1 --- Hardware and speed estimation : --- p.5-11 / Chapter 6. --- Implementation of self-timed ICT processor --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Implementation of Self-timed 2-D ICT processor (First version) --- p.6-3 / Chapter 6.2.1 --- 1-D ICT module --- p.6-4 / Chapter 6.2.2 --- Self-timed Transpose memory --- p.6-5 / Chapter 6.2.3 --- Layout Design --- p.6-8 / Chapter 6.3 --- Implementation of Self-timed 1-D ICT processor with fast algorithm (final version) --- p.6-9 / Chapter 6.3.1 --- I/O buffers and control units --- p.6-10 / Chapter 6.3.1.1 --- Input control --- p.6-11 / Chapter 6.3.1.2 --- Output control --- p.6-12 / Chapter 6.3.1.2.1 --- Self-timed Computational Block --- p.6-13 / Chapter 6.3.1.3 --- Handshake Control Unit --- p.6-14 / Chapter 6.3.1.4 --- Integer Execution Unit (IEU) --- p.6-18 / Chapter 6.3.1.5 --- Program memory and Instruction decoder --- p.6-20 / Chapter 6.3.2 --- Layout Design --- p.6-21 / Chapter 6.4 --- Specifications of the final version self-timed ICT chip --- p.6-22 / Chapter 7. --- Testing of Self-timed ICT processor --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Pin assignment of Self-timed 1 -D ICT chip --- p.7-2 / Chapter 7.3 --- Simulation --- p.7-3 / Chapter 7.4 --- Testing of Self-timed 1-D ICT processor --- p.7-5 / Chapter 7.4.1 --- Functional test --- p.7-5 / Chapter 7.4.1.1 --- Testing environment and results --- p.7-5 / Chapter 7.4.2 --- Transient Characteristics --- p.7-7 / Chapter 7.4.3 --- Comments on speed and power --- p.7-10 / Chapter 7.4.4 --- Determination of optimum delay control voltage --- p.7-12 / Chapter 7.5 --- Testing of delay element and other logic cells --- p.7-13 / Chapter 8. --- Conclusions --- p.8-1 / Bibliography / Appendices

Includes bibliographical references (leaves 277-284) Presents and discusses new design techniques for mixed analog-digital circuits with emphases on low power and small area for standard low-cost CMOS VLSI technology.