Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundamental concepts of digital logic design and VLSI design such as logic gates, MOS transistors, combinational and sequential logic circuits, and memory are presented in a simple, interactive and user friendly way to create interest in students towards engineering fields, especially Electrical Engineering and Computer Engineering. Most of the concepts are explained in this framework by taking the examples which we see in our daily lives. Some of the critical design concerns such as power and performance are presented in an interactive way to make sure that students can understand these significant concepts in an easy and user friendly way.

Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation. An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT. Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.

Recently, microelectronics designs have reached extremely high operating frequencies as well as very small die and package sizes. This has made signal integrity an important bottleneck in the design process, and resulted in the inclusion of signal integrity simulation in the computer aided design flow. However, such simulations are often difficult because in many cases it is impossible to derive analytical models for certain passive elements, and the only available data are frequency-domain measurements or full-wave simulations. Furthermore, at such high frequencies these components are distributed in nature and require a large number of poles to be properly characterized. Simple lumped equivalent circuits are therefore difficult to obtain, and more systematic approaches are required. In this thesis we study the Vector Fitting techniques for obtaining such equivalent model and propose a more streamlined approach for preserving passivity while maintaining accuracy.

The design of VLSI electronic circuits can be achieved at many different abstraction levels starting from system behavior to the most detailed, physical layout level. As the number of transistors in VLSI circuits is increasing, the complexity of the design is also increasing, and it is now beyond human ability to manage. Hence CAD (Computer Aided design) or EDA (Electronic Design Automation) tools are involved in the design. EDA or CAD tools automate the design, verification and testing of these VLSI circuits. In today’s market, there are many EDA tools available. However, they are very expensive and require high-performance platforms. One of the key challenges today is to select appropriate CAD or EDA tools which are open-source for academic purposes. This thesis provides a detailed examination of an open-source EDA tool called Electric VLSI Design system. An excellent and efficient CAD tool useful for students and teachers to implement ideas by modifying the source code, Electric fulfills these requirements. This thesis' primary objective is to explain the Electric software features and architecture and to provide various digital and analog designs that are implemented by this software for educational purposes. Since the choice of an EDA tool is based on the efficiency and functions that it can provide, this thesis explains all the analysis and synthesis tools that electric provides and how efficient they are. Hence, this thesis is of benefit for students and teachers that choose Electric as their open-source EDA tool for educational purposes.

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CAPES / Códigos corretores de erros estão presentes em quase todos os sistemas modernos de comunicação e armazenamento de dados. Erros durante essas operações são praticamente inevitáveis devido a ruído e interferências nos meios de comunicação e degradação dos meios de armazenamento. Quando um sistema exige alto desempenho, os correspondentes algoritmos (codificador e decodificador) são implementados em hardware. O projeto de pesquisa apresentado nesta tese, um chip dedicado para uma nova família de decodificadores baseados em conjuntos de informação, é parte de um amplo projeto que visa obter um decodificador com desempenho semelhante à decodificação de máxima verossimilhança (MLD), porém com hardware muito mais simples, demonstrando assim que o uso dessa técnica (decodificação por conjuntos de informação), até então proibitiva devido à complexidade do hardware, poderia tornar-se viável. Visando simplificar o hardware, o primeiro passo foi modificar o algoritmo original de Dorsch para reduzir o número de ciclos de clock necessários para decodificar uma mensagem. As principais modificações realizadas foram na redução de Gauss-Jordan e no número de palavras-código candidatas, consideravelmente reduzidas em relação ao algoritmo original de Dorsch. Este algoritmo modificado foi primeiramente implementado utilizando linguagem de descrição de hardware e avaliado em diferentes famílias de FPGAs, onde demonstrou-se o mesmo ser viável, mesmo para grandes códigos. O algoritmo foi implementado posteriormente em um chip dedicado (ASIC), utilizando tecnologia CMOS, a fim de completar a demonstração da viabilidade de sua implementação e uso efetivo. / Error-correcting codes are present in almost all modern data communications and data storage systems. Errors during these operations are practically inevitable because of noise and interference in communication channels and degradation of storage media. When topperformance is required, the corresponding algorithms (encoder and decoder) are implemented in hardware. The research project presented in this dissertation, a dedicated chip for a new family of decoders based on information sets, is part of a broad project targeting the development of a new decoder capable of achieving near maximum likelihood decoding (MLD) performance, however with a much simpler hardware, thus demonstrating that the use of this technique (decoding based on information sets), previously prohibitive due to the complexity of the hardware, could now be feasible. Aiming to simplify the hardware, the first step was to modify the original Dorsch algorithm to reduce the number of clock cycles needed to decode a message. The main modifications performed were in the Gauss Jordan elimination procedure and in the number of candidate codewords, which was highly reduced with respect to original Dorsch algorithm. This modified algorithm was first implemented using a hardware description language and evaluated in different FPGA families, where the viability was demonstrated. The algorithm was later implemented in a dedicated chip (ASIC) using CMOS technology in order to complete the demonstration of the feasibility of their implementation, and effective use.

CAPES / Códigos corretores de erros estão presentes em quase todos os sistemas modernos de comunicação e armazenamento de dados. Erros durante essas operações são praticamente inevitáveis devido a ruído e interferências nos meios de comunicação e degradação dos meios de armazenamento. Quando um sistema exige alto desempenho, os correspondentes algoritmos (codificador e decodificador) são implementados em hardware. O projeto de pesquisa apresentado nesta tese, um chip dedicado para uma nova família de decodificadores baseados em conjuntos de informação, é parte de um amplo projeto que visa obter um decodificador com desempenho semelhante à decodificação de máxima verossimilhança (MLD), porém com hardware muito mais simples, demonstrando assim que o uso dessa técnica (decodificação por conjuntos de informação), até então proibitiva devido à complexidade do hardware, poderia tornar-se viável. Visando simplificar o hardware, o primeiro passo foi modificar o algoritmo original de Dorsch para reduzir o número de ciclos de clock necessários para decodificar uma mensagem. As principais modificações realizadas foram na redução de Gauss-Jordan e no número de palavras-código candidatas, consideravelmente reduzidas em relação ao algoritmo original de Dorsch. Este algoritmo modificado foi primeiramente implementado utilizando linguagem de descrição de hardware e avaliado em diferentes famílias de FPGAs, onde demonstrou-se o mesmo ser viável, mesmo para grandes códigos. O algoritmo foi implementado posteriormente em um chip dedicado (ASIC), utilizando tecnologia CMOS, a fim de completar a demonstração da viabilidade de sua implementação e uso efetivo. / Error-correcting codes are present in almost all modern data communications and data storage systems. Errors during these operations are practically inevitable because of noise and interference in communication channels and degradation of storage media. When topperformance is required, the corresponding algorithms (encoder and decoder) are implemented in hardware. The research project presented in this dissertation, a dedicated chip for a new family of decoders based on information sets, is part of a broad project targeting the development of a new decoder capable of achieving near maximum likelihood decoding (MLD) performance, however with a much simpler hardware, thus demonstrating that the use of this technique (decoding based on information sets), previously prohibitive due to the complexity of the hardware, could now be feasible. Aiming to simplify the hardware, the first step was to modify the original Dorsch algorithm to reduce the number of clock cycles needed to decode a message. The main modifications performed were in the Gauss Jordan elimination procedure and in the number of candidate codewords, which was highly reduced with respect to original Dorsch algorithm. This modified algorithm was first implemented using a hardware description language and evaluated in different FPGA families, where the viability was demonstrated. The algorithm was later implemented in a dedicated chip (ASIC) using CMOS technology in order to complete the demonstration of the feasibility of their implementation, and effective use.