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As operating frequency increases and device sizes shrink, the complexity of current state-of-the-art designs has increased dramatically. One of the main contributors to this complexity is high speed interconnects. At high frequencies, interconnects become dominant contributors to signal degradation, and their effects such as delays, reflections, and crosstalk must be accurately simulated. Time domain analysis of such structures is however very difficult because, at high frequencies, they must be modeled as distributed transmission lines which, after discretization, result in very large networks. In order to improve the simulation efficiency of such structures, model order reduction has been proposed in the literature. Conventional model order reduction methods based on Krylov subspace have a number of limitations in many practical simulation problems. This restricts their usefulness in general commercial simulators. / In this thesis, a number of new reduction techniques were developed in order to address the key shortcomings of current model order reduction methods. Specifically a new approach for handling macromodels with a very large number of ports was developed, a multi-level reduction and sprasification method was proposed for regular as well as parametric macromodels, and finally a new time domain reduction method was presented for the macromodeling of nonlinear parametric systems. Using these approaches, CPU speedups of 1 to 2 orders of magnitude were obtained.

Wires have become a major source of bottleneck in current VLSI designs, and wire length prediction is therefore essential to overcome these bottlenecks. Wire length prediction is broadly classified into two types: macroscopic prediction, which is the prediction of wire length distribution, and microscopic prediction, which is the prediction of individual wire lengths. The objective of this thesis is to develop a clear understanding of limitations to both macroscopic and microscopic a priori, post-placement, pre-routing wire length predictions, and thereby develop better wire length prediction models. Investigations carried out to understand the limitations to macroscopic prediction reveal that, in a given design (i) the variability of the wire length distribution increases with length and (ii) the use of Rent s rule with a constant Rent s exponent p, to calculate the terminal count of a given block size, limits the accuracy of the results from a macroscopic model. Therefore, a new model for the parameter p is developed to more accurately reflect the terminal count of a given block size in placement, and using this, a new more accurate macroscopic model is developed. In addition, a model to predict the variability is also incorporated into the macroscopic model. Studies to understand limitations to microscopic prediction reveal that (i) only a fraction of the wires in a given design are predictable, and these are mostly from shorter nets with smaller degrees and (ii) the current microscopic prediction models are built based on the assumption that a single metric could be used to accurately predict the individual length of all the wires in a design. In this thesis, an alternative microscopic model is developed for the predicting the shorter wires based on a hypothesis that there are multiple metrics that influence the length of the wires. Three different metrics are developed and fitted into a heuristic classification tree framework to provide a unified and more accurate microscopic model.

Layered multiconductor coupled slot and strip-slot structures are characterized by introducing the full-wave modal analysis as well as the quasi-TEM spectral domain technique. In the modal analysis, the electric and magnetic fields are constructed in terms of modal fields in different regions. Application of the boundary conditions at interfaces for the tangential components of the electric and magnetic fields results in the dyadic Green's function, which interrelates the tangential currents and electric fields at the boundaries of the layered structure. The slot fields and strip currents are expanded in terms of a set of known basis functions with unknown coefficients. Use of the Galerkin method leads to a set of algebraic equations. The non-trivial solutions for the propagation constants are found by setting the determinant of the algebraic equations equal to zero. All the other normal mode parameters including the modal impedances, the field and current eigenvectors are then computed by using the solutions of the propagation constants. In the quasi-TEM analysis, the Laplace equation is transformed to an ordinary differential equation in the spectral domain, the solution of which together with the boundary conditions yields the Green's function which interrelates the potential and the charge distribution at the interfaces of the layered structure. The charge distribution is expanded in terms of known functions with unknown coefficients which are subsequently evaluated by applying the Galerkin method. Once the charge distribution is found, the quasi-TEM characteristics of the coupled strip-slot structures are readily calculated. Different impedance definitions proposed in the literature for multiple coupled line structures are discussed. The only useful impedance definition in the design of microwave and millimeter-wave circuits is the one that results in a symmetric impedance matrix for a coupled line structure in a lossless, isotropic, and linear medium. The normal mode impedance definition as based on the reciprocity is used to systematically study the impedance characteristics of various coupled slot structures for the first time, which together with the propagation characteristics are used to compute equivalent circuit models for ideal coupled line structures. The applications of the coupled slot and strip-slot structures are illustrated through design examples of enhanced couplers and power dividers consisting of coupled line multiports. Time domain simulation of coupled multiconductor structures with slotted ground planes is also presented to exemplify the applications of the techniques developed in this thesis to layered interconnects and packaging structures in high-speed circuits. Some novel techniques to reduce the crosstalk noise in those structures are proposed with theoretical examples and experimental results. / Graduation date: 1994

Synchronization is one of the important issues in digital system design. While other approaches have been intriguing, up until now a globally clocked timing discipline has been the dominant design philosophy. However, we have reached the point, with advances in technology, where other options should be given serious consideration. VLSI promises great processing power at low cost. This increase in computation power has been obtained by scaling the digital IC process. But as this scaling continues, it is doubtful that the advantages of faster devices can be fully exploited. This is because the clock periods are getting much smaller in relation to the interconnect propagation delays, even within a single chip and certainly at the board and backplane level. In this thesis, some alternative approaches to synchronization in digital system design are described and developed. We owe these techniques to a long history of effort in both digital computational system design as well as digital communication system design. The latter field is relevant because large propagation delays have always been a dominant consideration in its design methods. Asynchronous design gives better performance than comparable synchronous design in situations for which a global synchronization with a high speed clock becomes a constraint for greater system throughput. Asynchronous circuits with unbounded gate delays, or self-timed digital circuit can be designed by employing either of two request-acknowledge protocols 4-cycle and 2-cycle. We will also present an alternative approach to the problem of mapping computation algorithms directly into asynchronous circuits. Data flow graph or language is used to describe the computation algorithms. The data flow primitives have been designed using both the 2-cycle and 4-cycle signaling schemes which are compared in terms of performance and transistor count. The 2-cycle implementations prove to be better than their 4-cycle counterparts. A promising application of self-timed design is in high performance DSP systems. Since there is no global constraint of clock distribution, localized forwardonly connection allows computation to be extended and sped up using pipelining. A decimation filter was designed and simulated to check the system level performance of the two protocols. Simulations were carried out using VHDL for high level definition of the design. The simulation results will demonstrate not only the efficacy of our synthesis procedure but also the improved efficiency of the 2-cycle scheme over the 4- cycle scheme. / Graduation date: 1994

Bibliography: leaves 188-203. / xxii, 203 leaves : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / In this thesis insect vision principles are applied to the main mechanism for motion detection. Advanced VLSI technologies are employed for designing smart micro-sensors in which the imager and processor are integrated into one monolithic device. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1996

Bibliography: leaves 216-224. / xix, 224 leaves : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / This thesis describes a collection of design techniques engineered for high speed operation. A new gate representation is proposed to better reflect their functionality in an asynchronous domain. Two microprocessors (ECSTAC and ECSCESS) are implemented as an illustration of these design techniques. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1998?