This thesis deals primarily with the problem of soft-error tolerance in digital machines. The possible sources of soft errors are reviewed. It is shown that the significance of ionizing radiation increases with the scaling down of MOS technologies. The characteristics of electromagnetic interference sources are also discussed. After presenting the conventional methods of dealing with soft errors, a new approach to this problem is suggested. The new approach, called Soft-Error Filtering (SEF), consists of filtering every output of the logic before latching it, in such a way that a transient injected into a machine does not change the final result of an operation. An analysis of the reduction in the error rate that is obtained by using SEF is presented. For example, this analysis demonstrates that the error rate due to alpha particles generated by the decay of radioactive elements becomes negligible. A great deal of attention is devoted to the design of filtering latches which is an essential component for implementing SEF machines. Three structures are considered and a CMOS implementation is proposed in each case. The double-filter latch is the best of the three implementations. It features a nearly optimum performance in the time domain and it is relatively insensitive to process fluctuations. An overhead analysis demonstrates that SEF usually results in a small overhead, both in area and in time simultaneously. In conclusion, SEF is the best approach to the problem of designing a machine tolerant to short transients.

Microwave circuit design including the design of Interconnect circuits are proving to be a very hard and complex process where the use of CAD tools is becoming more essential to the reduction in design time and in providing more accurate results. Space mapping methods, the relatively new and very efficient way of optimization which are used in microwave filters and structures will be investigated in this thesis and applied to the time domain optimization of digital interconnects. The main advantage is that the optimization is driven using simpler models called coarse models that would approximate the more complex fine model of the real system, which provide a better insight to the problem and at the same time reduce the optimization time. The results are always mapped back to the real system and a relation/mapping is found between both systems which would help the convergence time. In this thesis, we study the optimization of interconnects where we build certain practical error functions to evaluate performance in the time domain. The space mapping method is formulated to avoid problems found in the original formulation where we apply some necessary modifications to the Trust Region Aggressive Space Mapping TRASM for it to be applicable to the design process in time domain. This new method modified TRASM or MTRASM is then evaluated and tested on multiple circuits with different configuration and the results are compared to the results obtained from TRASM.

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As modern integrated-circuit (IC) technology advances, the level of integration increases, and so too does the clock speed of on-chip signals. As a result, signal integrity has become a major issue on which the circuit performance is largely based. Clock jitter is one of the main issues of signal integrity, and it has become one of the most important circuit limitations. / While extensive research is on-going to reduce clock jitter in ICs, researchers have also been actively involved in discovering ways to characterize it through applications of new time measurement units, or TMUs for short. A number of TMUs have been designed with resolutions down to the picosecond range, among which the time-to-voltage converter (TVC) is a very popular family of circuits used for making highly precise and accurate time measurements. These circuits are popular due to their excellent linearity properties and their ease of fabrication. Nonetheless, these circuits suffer from metastability issues, limiting the lower end of their measurement range. / This thesis first reviews the past TMU circuits, and then presents a TVC architecture that solves the metastability problem. In addition, pipelined operation is added to further increase the throughput of the design. The resolution of the TVC is made adjustable such that it can be used as a stand-alone TMU for different types of applications. The proposed TVC is both verified in simulation and experimentally using a custom designed circuit in a standard 0.18 microm CMOS process supplied by TSMC. Finally, a calibration method is included to further improve the linearity of the overall design.

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