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In this dissertation, we propose two fault simulators, called HOPE and HOPE2, and an autolllatic test pattern generator (ATPG), called ATHENA, for synchronous and asynchronous sequential circuits. HOPE is a parallel fault simulator for synchronous sequential circuits. In HOPE, a packet of 32 faults is simulated in parallel. Several new heuristics are employed in HOPE to accelerate the parallel fault simulation. The heuristics are 1) a reduction of faults to be simulated in parallel, 2) a new fault injection method called functional fault injection, and J) a combination of static and dynamic fault ordering methods. According to our experiments, HOPE is about 2.2 times, on the average, faster than a competing fault simulator, called PROOFS (1]--[2]. for 16 ISCAS89 benchmark circuits [3]. HOPE2 and ATHENA are a fault simulator and an A TPG for asynchronous sequential circuits, respectively. The key idea employed in HOPE2 and ATHENA is 10 transform an asynchronous sequential circuit into a synchronous sequential circuit through remodeling memory elements. We proposed various modeling techniques which transform any asynchronous sequential circuit into a synChronous sequential circuit. Once an asyncllfonous circuit is transformed into a synchronous circuit, various techniques developed for synchronous sequential circuits are employed in HOPE2 and ATHENA. HOPE2 employs the parallel simulation techniques of HOPE. ATHENA employs the back algorithm [4] for test generation, and the parallel fault simulation teChnique for fault simulation. HOPE2 and ATHENA can manage industrial circuits consisting of latches, flip-flops with set/reset, tristate gates, BUS elements, bi-directional I/O pins, mutiplexers, ROMs and RAMs. OUf experimental results on various industrial circuits show that HOPE2 is about two times faster than a commercial fault simulator, the Verifault fault simulator of Cadence, while requiring much smaller memory size. ATHENA also shows high performance for various industrial circuits. / Ph. D.

A formal behavioral test generation algorithm, called the B-algorithm, is presented together with a behavioral VHDL model and a realistic behavioral fault model. Using the behavioral VHDL model, a behavioral VHDL circuit description is represented as a set of equivalent process Statements and connections among them. The behavioral fault model consists of three types of behavioral faults (behavioral stuck-at faults, behavioral stuck-open faults, and micro-operation faults) which well represent faulty behaviors of a digital circuit. The behavioral VHDL model and the behavioral fault model improve the efficiency of test generation by reducing the size of the domain searched during the test generation procedure. The B-algorithm generates tests directly from behavioral VHDL circuit descriptions using three basic test generation operations (activation, propagation, and justification), which are systematically executed by manipulating three data structures (B-frontier, J-frontier, and A-queue). Rules for the test generation operations are formally defined using the concepts of two-phase activation and two-phase propagation. The difference between simulation semantics and test generation semantics is discussed, and a method of efficiently assigning time periods without being affected by simulation semantics is proposed. A method of handling bus resolution functions, reconvergent fanout, and feedback loops during test generation is discussed. Two-phase testing, a testing strategy where a fault is detected using two consecutive test sequences, is introduced and 1s formally incorporated into the B-algorithm. / Ph. D.

As advances in very large scale integration (VLSI) technology lead to higher levels of circuit integration and new design styles and fabrication processes, traditional test generation techniques fail to adequately address the problems of how to (l) accurately represent the structure of design styles and physical faults, and (2) manage the high computational costs and memory resource requirements caused by the complexity of VLSI. This research investigates a modular, hierarchical approach to test generation for combinational complementary metal oxide semiconductor (CMOS) circuits that effectively deals with these issues. Circuits are modeled using multi-level descriptions to handle large circuit sizes while maintaining an effective balance between accuracy and complexity. Object-oriented analysis and design techniques are used in the development of a hierarchical test generation application implemented using C++. In doing this, the primary objectives were to produce a easily maintainable system, provide an extensible framework for test generation supporting the straightforward incorporation of new types of circuit primitives and faults, and retain the same level of computational efficiency that can be achieved using a procedural language such as C. Characteristics of the object-oriented hierarchical test generation application, such as expandability and run-time efficiency, are compared to those of a standard gate-level test generation program implemented using C and a procedural design approach. / Ph. D.

Traditional test generation techniques for digital circuits have been rendered inadequate by the increasing levels of integration achieved by VLSI technology. This thesis presents a test generation algorithm, the E-algorithm, that generates tests for circuits described using the VHDL Hardware Description Language. A fault model has been developed that addresses data path faults, faults in control structures, and faults in functional operators. The E-algorithm is able to generate tests for all modeled fault types, and handles a wide variety of circuit types, including sequential circuits. The algorithm has been implemented; preliminary results are given. / Master of Science

In this thesis, new methods to handle reconvergent fanout and feed-back during behavioral level test generation are proposed. These methods have been implemented - into a previously developed automatic test generator. The improved test generator was tested on five behavioral circuit models. For circuits with the reconvergent fanout situation, the improved test generator can generate tests completely automatically. For circuits with feed-back, user assistance in a circuit initialization step is required. Some suggestions for future development for the test generator are discussed. Examples on how to use the improved test generator are presented. / Master of Science

Delay fault testing of high speed VLSI circuits is becoming increasingly important. This thesis presents an Automatic Test Pattern Generator (ATPG), called TENOR, for transition faults. Transition faults are a special case of gate delay faults. Test generation is based on the FAN algorithm. The approach taken in this thesis is to map a transition fault into two stuck-at faults, and then generate test patterns for the stuck-at faults. A fault simulator, based on parallel pattern single fault propagation, was also developed. The problem of generating both non-robust and robust tests has been addressed. Experimental results indicate that TENOR is one of the fastest ATPGs among similar previous works, with comparable fault coverage. Experiments were also done to determine the effectiveness of stuck-at test sets and random test patterns in detecting transition faults. / Master of Science

An implementation of an interactive design rule checker is described in this thesis. Corner-based design rule checking algorithm is used for the implementation. Due to the locality of checking mechanism of the corner-based algorithm, it is suitable for hierarchical and interactive local design rule checking. It also allows the various design rules to be specified very easily. Interactive operations are devised so that the design rule checker can be invoked from inside the layout editor. All the information about the violation, such as position, type of violation, and symbol definition name are provided in an interactive manner. In order to give full freedom to the user to choose the scope of checking, three options, "Flattening", "Unflattening" and "User-defined window" are implemented in creating the database to be checked. The "User-defined window" option allows hierarchical design rule checking on a design which contains global rectangles. Using these three options, very efficient hierarchical checking can be performed. / Master of Science / incomplete_metadata