by Yuen-Pat Lau. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1997. / Includes bibliographical references (leaves 127-[129]). / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Interconnects in Circuits --- p.1 / Chapter 1.2 --- Propagating Waves on Interconnects --- p.4 / Chapter 2 --- Theory: FDTD --- p.6 / Chapter 2.1 --- Modelling Microstrips in FDTD Mesh Space --- p.6 / Chapter 2.2 --- FDTD Implementation of a Unit Cell --- p.8 / Chapter 2.3 --- FDTD Implementation of a Lumped Element --- p.12 / Chapter 2.4 --- FDTD Implementation of a Circuit --- p.14 / Chapter 3 --- Theory: TDMS --- p.20 / Chapter 3.1 --- FDTD Circuit Simulation --- p.20 / Chapter 3.2 --- TDMS: Microstrip Characterization --- p.22 / Chapter 3.3 --- TDMS: Parameter Extraction --- p.23 / Chapter 3.4 --- TDMS: Circuit Simulation --- p.26 / Chapter 4 --- TDMS Simulations --- p.30 / Chapter 4.1 --- Example One: Loaded Diode --- p.30 / Chapter 4.2 --- Example Two: Unbalanced Mixer --- p.38 / Chapter 5 --- TDR Experiments --- p.54 / Chapter 5.1 --- Example Three: Uniform Microstrip --- p.54 / Chapter 5.2 --- Example Four: Coupled Microstrip --- p.61 / Chapter 5.3 --- Example Five: Change-in-width Microstrip --- p.67 / Chapter 6 --- Conclusion --- p.78 / Chapter 7 --- Program Listing --- p.80 / Chapter 7.1 --- Example Two: Unbalanced Mixer --- p.80 / Chapter 7.2 --- Example Five: Change-in-width Microstrip --- p.110 / Bibliography --- p.127

Sze, Chin Ngai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 80-84) and index. / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Curriculum Vitae --- p.iv / List of Figures --- p.ix / List of Tables --- p.xii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Aims --- p.1 / Chapter 1.2 --- Contribution --- p.8 / Chapter 1.3 --- Organization of Dissertation --- p.10 / Chapter 2 --- Definitions and Notations --- p.11 / Chapter 3 --- Literature Review --- p.15 / Chapter 3.1 --- Logic Reconstruction --- p.15 / Chapter 3.1.1 --- SIS: A System for Sequential and Combinational Logic Synthesis --- p.16 / Chapter 3.2 --- ATPG-based Alternative Wiring --- p.17 / Chapter 3.2.1 --- Redundancy Addition and Removal for Logic Optimization --- p.18 / Chapter 3.2.2 --- Perturb and Simplify Logic Optimization --- p.18 / Chapter 3.2.3 --- REWIRE --- p.21 / Chapter 3.2.4 --- Implication-tree Based Alternative Wiring Logic Trans- formation --- p.22 / Chapter 3.3 --- Graph-based Alternative Wiring --- p.24 / Chapter 4 --- Implication Based Alternative Wiring Logic Transformation --- p.25 / Chapter 4.1 --- Source Node Implication --- p.25 / Chapter 4.1.1 --- Introduction --- p.25 / Chapter 4.1.2 --- Implication Relationship and Implication-tree --- p.25 / Chapter 4.1.3 --- Selection of Alternative Wire Based on Implication-tree --- p.29 / Chapter 4.1.4 --- Implication-tree Based Logic Transformation --- p.32 / Chapter 4.2 --- Destination Node Implication --- p.35 / Chapter 4.2.1 --- Introduction --- p.35 / Chapter 4.2.2 --- Destination Node Relationship --- p.35 / Chapter 4.2.3 --- Destination Node Implication-tree --- p.39 / Chapter 4.2.4 --- Selection of Alternative Wire --- p.41 / Chapter 4.3 --- The Algorithm --- p.43 / Chapter 4.3.1 --- IB AW Implementation --- p.43 / Chapter 4.3.2 --- Experimental Results --- p.43 / Chapter 4.4 --- Conclusion --- p.45 / Chapter 5 --- Graph Based Alternative Wiring Logic Transformation --- p.47 / Chapter 5.1 --- Introduction --- p.47 / Chapter 5.2 --- Notations and Definitions --- p.48 / Chapter 5.3 --- Alternative Wire Patterns --- p.50 / Chapter 5.4 --- Construction of Minimal Patterns --- p.54 / Chapter 5.4.1 --- Minimality of Patterns --- p.54 / Chapter 5.4.2 --- Minimal Pattern Formation --- p.56 / Chapter 5.4.3 --- Pattern Extraction --- p.61 / Chapter 5.5 --- Experimental Results --- p.63 / Chapter 5.6 --- Conclusion --- p.63 / Chapter 6 --- Logic Optimization by GBAW --- p.66 / Chapter 6.1 --- Introduction --- p.66 / Chapter 6.2 --- Logic Simplification --- p.67 / Chapter 6.2.1 --- Single-Addition-Multiple-Removal by Pattern Feature . . --- p.67 / Chapter 6.2.2 --- Single-Addition-Multiple-Removal by Combination of Pat- terns --- p.68 / Chapter 6.2.3 --- Single-Addition-Single-Removal --- p.70 / Chapter 6.3 --- Incremental Perturbation Heuristic --- p.71 / Chapter 6.4 --- GBAW Optimization Algorithm --- p.73 / Chapter 6.5 --- Experimental Results --- p.73 / Chapter 6.6 --- Conclusion --- p.76 / Chapter 7 --- Conclusion --- p.78 / Bibliography --- p.80 / Chapter A --- VLSI Design Cycle --- p.85 / Chapter B --- Alternative Wire Patterns in [WLFOO] --- p.87 / Chapter B.1 --- 0-local Pattern --- p.87 / Chapter B.2 --- 1-local Pattern --- p.88 / Chapter B.3 --- 2-local Pattern --- p.89 / Chapter B.4 --- Fanout-reconvergent Pattern --- p.90 / Chapter C --- New Alternative Wire Patterns --- p.91 / Chapter C.1 --- Pattern Cluster C1 --- p.91 / Chapter C.1.1 --- NAND-NAND-AND/NAND;AND/NAND --- p.91 / Chapter C.1.2 --- NOR-NOR-OR/NOR;AND/NAND --- p.92 / Chapter C.1.3 --- AND-NOR-OR/NOR;OR/NOR --- p.95 / Chapter C.1.4 --- OR-NAND-AND/NAND;AND/NAND --- p.95 / Chapter C.2 --- Pattern Cluster C2 --- p.98 / Chapter C.3 --- Pattern Cluster C3 --- p.99 / Chapter C.4 --- Pattern Cluster C4 --- p.104 / Chapter C.5 --- Pattern Cluster C5 --- p.105 / Glossary --- p.106 / Index --- p.108

Han Wei. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 60-61). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.ii / Acknowledgements --- p.iii / Contents --- p.iv / List of Figures --- p.vi / List of Tables --- p.vii / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1. --- Speech Recognition --- p.1 / Chapter 1.2. --- ASIC Design with HDLs --- p.3 / Chapter Chapter 2 --- Theory of HMM-Based Speech Recognition --- p.6 / Chapter 2.1. --- Speaker-Dependent and Speaker-Independent --- p.6 / Chapter 2.2. --- Frame and Feature Vector --- p.6 / Chapter 2.3. --- Hidden Markov Model --- p.7 / Chapter 2.3.1. --- Markov Model --- p.8 / Chapter 2.3.2. --- Hidden Markov Model --- p.9 / Chapter 2.3.3. --- Elements of an HMM --- p.10 / Chapter 2.3.4. --- Types of HMMs --- p.11 / Chapter 2.3.5. --- Continuous Observation Densities in HMMs --- p.13 / Chapter 2.3.6. --- Three Basic Problems for HMMs --- p.15 / Chapter 2.4. --- Probability Evaluation --- p.16 / Chapter 2.4.1. --- The Viterbi Algorithm --- p.17 / Chapter 2.4.2. --- Alternative Viterbi Implementation --- p.19 / Chapter Chapter 3 --- HMM-based Isolated Word Recognizer Design Methodology …… --- p.20 / Chapter 3.1. --- Speech Recognition Based On Single Mixture --- p.23 / Chapter 3.2. --- Speech Recognition Based On Double Mixtures --- p.25 / Chapter Chapter 4 --- VLSI Implementation of the Speech Recognizer --- p.29 / Chapter 4.1. --- The System Requirements --- p.29 / Chapter 4.2. --- Implementation of a Speech Recognizer with a Single-Mixture HMM --- p.30 / Chapter 4.3. --- Implementation of a Speech Recognizer with a Double-Mixture HMM --- p.39 / Chapter 4.4. --- Extend Usage in High Order Mixtures HMM --- p.46 / Chapter 4.5. --- Pipelining and the System Timing --- p.50 / Chapter Chapter 5 --- Simulation and IC Testing --- p.53 / Chapter 5.1. --- Simulation Result --- p.53 / Chapter 5.2. --- Testing --- p.55 / Chapter Chapter 6 --- Discussion and Conclusion --- p.58 / Reference --- p.60 / Appendix I Verilog Code of the Double-Mixture HMM Based Speech Recognition IC (RTL Level) --- p.62 / Subtracter --- p.62 / Multiplier --- p.63 / Core_Adder --- p.65 / Register for X --- p.66 / Subtractor and Comparator --- p.67 / Shifter --- p.68 / Look-Up Table --- p.71 / Register for Constants --- p.79 / Register for Scores --- p.80 / Final Score Register --- p.84 / Controller --- p.86 / Top --- p.97 / Appendix II Chip Microphotograph --- p.103 / Appendix III Pin Assignment of the Speech Recognition IC --- p.104 / Appendix IV The Testing Board of the IC --- p.108

Ma, Qiang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 78-80). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Floorplanning --- p.2 / Chapter 1.3 --- Motivations --- p.4 / Chapter 1.4 --- Design Implementation of Voltage Islands --- p.5 / Chapter 1.5 --- Problem Formulation --- p.8 / Chapter 1.6 --- Progress on the Problem --- p.10 / Chapter 1.7 --- Contributions --- p.12 / Chapter 1.8 --- Thesis Organization --- p.14 / Chapter 2 --- Literature Review on MSV --- p.15 / Chapter 2.1 --- Introduction --- p.15 / Chapter 2.2 --- MSV at Post-floorplan/Post Placement Stage --- p.16 / Chapter 2.2.1 --- """Post-Placement Voltage Island Generation under Performance Requirement""" --- p.16 / Chapter 2.2.2 --- """Post-Placement Voltage Island Generation""" --- p.18 / Chapter 2.2.3 --- """Timing-Constrained and Voltage-Island-Aware Voltage Assignment""" --- p.19 / Chapter 2.2.4 --- """Voltage Island Generation under Performance Requirement for SoC Designs""" --- p.20 / Chapter 2.2.5 --- """An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning""" --- p.21 / Chapter 2.3 --- MSV at Floorplan/Placement Stage --- p.22 / Chapter 2.3.1 --- """Architecting Voltage Islands in Core-based System-on-a- Chip Designs""" --- p.22 / Chapter 2.3.2 --- """Voltage Island Aware Floorplanning for Power and Timing Optimization""" --- p.23 / Chapter 2.4 --- Summary --- p.27 / Chapter 3 --- MSV Driven Floorplanning --- p.29 / Chapter 3.1 --- Introduction --- p.29 / Chapter 3.2 --- Problem Formulation --- p.32 / Chapter 3.3 --- Algorithm Overview --- p.33 / Chapter 3.4 --- Optimal Island Partitioning and Voltage Assignment --- p.33 / Chapter 3.4.1 --- Voltage Islands in Non-subtrees --- p.35 / Chapter 3.4.2 --- Proof of Optimality --- p.36 / Chapter 3.4.3 --- Handling Island with Power Down Mode --- p.37 / Chapter 3.4.4 --- Speedup in Implementation and Complexity --- p.38 / Chapter 3.4.5 --- Varying Background Chip-level Voltage --- p.39 / Chapter 3.5 --- Simulated Annealing --- p.39 / Chapter 3.5.1 --- Moves --- p.39 / Chapter 3.5.2 --- Cost Function --- p.40 / Chapter 3.6 --- Experimental Results --- p.40 / Chapter 3.6.1 --- Extension to Minimize Level Shifters --- p.45 / Chapter 3.6.2 --- Extension to Consider Power Network Routing --- p.46 / Chapter 3.7 --- Summary --- p.46 / Chapter 4 --- MSV Driven Floorplanning with Timing --- p.49 / Chapter 4.1 --- Introduction --- p.49 / Chapter 4.2 --- Problem Formulation --- p.52 / Chapter 4.3 --- Algorithm Overview --- p.56 / Chapter 4.4 --- Voltage Assignment Problem --- p.56 / Chapter 4.4.1 --- Lagrangian Relaxation --- p.58 / Chapter 4.4.2 --- Transformation into the Primal Minimum Cost Flow Problem --- p.60 / Chapter 4.4.3 --- Cost-Scaling Algorithm --- p.64 / Chapter 4.4.4 --- Solution Transformation --- p.66 / Chapter 4.5 --- Simulated Annealing --- p.69 / Chapter 4.5.1 --- Moves --- p.69 / Chapter 4.5.2 --- Speeding up heuristic --- p.69 / Chapter 4.5.3 --- Cost Function --- p.70 / Chapter 4.5.4 --- Annealing Schedule --- p.71 / Chapter 4.6 --- Experimental Results --- p.71 / Chapter 4.7 --- Summary --- p.72 / Chapter 5 --- Conclusion --- p.76 / Bibliography --- p.80

Leung, Chi Kwan. / Thesis submitted in: December 2007. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 66-68). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Literature Review on Fixed-outline Floorplanning --- p.5 / Chapter 2.1 --- General Floorplanning --- p.5 / Chapter 2.1.1 --- Simulated Annealing --- p.6 / Example - Normalized Polish Expression --- p.9 / Example - Sequence Pair Representation --- p.15 / Example - Corner Block List --- p.19 / Chapter 2.1.2 --- Genetic Algorithm --- p.24 / Chapter 2.1.3 --- Mixed Integer Linear Programming --- p.25 / Chapter 2.1.4 --- Geometric Programming --- p.25 / Chapter 2.1.5 --- Discussion --- p.26 / Advantages of using Simulated Annealing --- p.26 / Disadvantages of using Simulated Annealing --- p.27 / Chapter 2.2 --- Fixed-outline Floorplanning --- p.28 / Chapter 2.2.1 --- Motivation --- p.28 / Chapter 2.2.2 --- Dimension Based Cost Function --- p.30 / Chapter 2.2.3 --- Aspect Ratio Based Cost Function --- p.32 / Chapter 2.2.4 --- Evolutionary Search --- p.33 / Chapter 2.2.5 --- Instance Augmentation --- p.35 / Chapter 3 --- Predictive Rating with Fixed Outline Constraints --- p.39 / Chapter 3.1 --- Introduction --- p.39 / Chapter 3.2 --- Motivation --- p.40 / Chapter 3.3 --- Predictive Rating Scheme --- p.44 / Chapter 3.3.1 --- Area --- p.45 / Chapter 3.3.2 --- Dimensions --- p.46 / Chapter 3.3.3 --- Aspect Ratio --- p.47 / Chapter 3.3.4 --- Overall Equation for Predictive Rating --- p.48 / Chapter 3.4 --- Integration into the Floorplanner --- p.49 / Chapter 3.5 --- Experimental Results --- p.50 / Chapter 3.5.1 --- Accuracy of Predictive Rating --- p.50 / Chapter 3.5.2 --- Test One --- p.52 / Chapter 3.5.3 --- Test Two --- p.57 / Chapter 3.6 --- Conclusion --- p.61 / Chapter 4 --- Conclusion --- p.64 / Bibliography --- p.66

Jiang, Yan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (p. 87-92). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Physical Design --- p.2 / Chapter 1.2 --- Floorplanning --- p.6 / Chapter 1.2.1 --- Floorplanning Objectives --- p.7 / Chapter 1.2.2 --- Common Approaches --- p.8 / Chapter 1.3 --- Motivations and Contributions --- p.14 / Chapter 1.4 --- Organization of the Thesis --- p.15 / Chapter 2 --- Literature Review on BDF --- p.17 / Chapter 2.1 --- Zero-Bend BDF --- p.17 / Chapter 2.1.1 --- BDF Using the Sequence-Pair Representation --- p.17 / Chapter 2.1.2 --- Using B*-Tree and Fast SA --- p.20 / Chapter 2.2 --- Two-Bend BDF --- p.22 / Chapter 2.3 --- TCG-Based Multi-Bend BDF --- p.25 / Chapter 2.3.1 --- Placement Constraints for Bus --- p.26 / Chapter 2.3.2 --- Bus Ordering --- p.28 / Chapter 2.4 --- Bus-Pin-Aware BDF --- p.30 / Chapter 2.5 --- Summary --- p.33 / Chapter 3 --- Fixed-Outline BDF --- p.35 / Chapter 3.1 --- Introduction --- p.35 / Chapter 3.2 --- Problem Formulation --- p.36 / Chapter 3.3 --- The Overview of Our Approach --- p.36 / Chapter 3.4 --- Partitioning --- p.37 / Chapter 3.4.1. --- The Overview of Partitioning --- p.38 / Chapter 3.4.2 --- Building a Hypergraph G --- p.39 / Chapter 3.5 --- Floorplaiining with Bus Routing --- p.43 / Chapter 3.5.1 --- Find Bus Routes --- p.43 / Chapter 3.5.2 --- Realization of Bus Routes --- p.48 / Chapter 3.5.3 --- Details of the Annealing Process --- p.50 / Chapter 3.6 --- Handle Fixed-Outline Constraints --- p.52 / Chapter 3.7 --- Bus Layout --- p.52 / Chapter 3.8 --- Experimental Results --- p.56 / Chapter 3.9 --- Summary --- p.61 / Chapter 4 --- Fixed-Outline BDF with L-shape bus --- p.63 / Chapter 4.1 --- Introduction --- p.63 / Chapter 4.2 --- Problem Formulation --- p.64 / Chapter 4.3 --- Our Approach --- p.65 / Chapter 4.3.1 --- Bus Routability Checking --- p.67 / Chapter 4.3.2 --- Details of the Annealing Process --- p.79 / Chapter 4.4 --- Experimental Results --- p.79 / Chapter 4.5 --- Summary --- p.82 / Chapter 5 --- Conclusion --- p.85 / Bibliography --- p.92

Tian, Haitong. / Chinese abstract is on unnumbered page. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (p. 65-74). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Our Contributions --- p.2 / Chapter 1.3 --- Organization of the Thesis --- p.3 / Chapter 2 --- Background Study --- p.4 / Chapter 2.1 --- Traditional Clock Routing Problem --- p.4 / Chapter 2.2 --- Tree-Based Clock Routing Algorithms --- p.5 / Chapter 2.2.1 --- Clock Routing Using H-tree --- p.5 / Chapter 2.2.2 --- Method of Means and Medians(MMM) --- p.6 / Chapter 2.2.3 --- Geometric Matching Algorithm (GMA) --- p.8 / Chapter 2.2.4 --- Exact Zero-Skew Algorithm --- p.9 / Chapter 2.2.5 --- Deferred Merge Embedding (DME) --- p.10 / Chapter 2.2.6 --- Boundary Merging and Embedding (BME) Algorithm --- p.14 / Chapter 2.2.7 --- Planar Clock Routing Algorithm --- p.17 / Chapter 2.2.8 --- Useful-skew Tree Algorithm --- p.18 / Chapter 2.3 --- Non-Tree Clock Distribution Networks --- p.19 / Chapter 2.3.1 --- Grid (Mesh) Structure --- p.20 / Chapter 2.3.2 --- Spine Structure --- p.20 / Chapter 2.3.3 --- Hybrid Structure --- p.21 / Chapter 2.4 --- Post-grid Clock Routing Problem --- p.22 / Chapter 2.5 --- Limitations of the Previous Work --- p.24 / Chapter 3 --- Post-Grid Clock Routing Problem --- p.26 / Chapter 3.1 --- Introduction --- p.26 / Chapter 3.2 --- Problem Definition --- p.27 / Chapter 3.3 --- Our Approach --- p.30 / Chapter 3.3.1 --- Delay-driven Path Expansion Algorithm --- p.31 / Chapter 3.3.2 --- Pre-processing to Connect Critical ports --- p.34 / Chapter 3.3.3 --- Post-processing to Reduce Capacitance --- p.36 / Chapter 3.4 --- Experimental Results --- p.39 / Chapter 3.4.1 --- Experiment Setup --- p.39 / Chapter 3.4.2 --- Validations of the Delay and Slew Estimation --- p.39 / Chapter 3.4.3 --- Comparisons with the Tree Grow (TG) Approach --- p.41 / Chapter 3.4.4 --- Lowest Achievable Delays --- p.42 / Chapter 3.4.5 --- Simulation Results --- p.42 / Chapter 4 --- Non-tree Based Post-Grid Clock Routing Problem --- p.44 / Chapter 4.1 --- Introduction --- p.44 / Chapter 4.2 --- Handling Ports with Large Load Capacitances --- p.46 / Chapter 4.2.1 --- Problem Ports Identification --- p.47 / Chapter 4.2.2 --- Non-Tree Construction --- p.47 / Chapter 4.2.3 --- Wire Link Selection --- p.48 / Chapter 4.3 --- Path Expansion in Non-tree Algorithm --- p.51 / Chapter 4.4 --- Limitations of the Non-tree Algorithm --- p.51 / Chapter 4.5 --- Experimental Results --- p.51 / Chapter 4.5.1 --- Experiment Setup --- p.51 / Chapter 4.5.2 --- Validations of the Delay and Slew Estimation --- p.52 / Chapter 4.5.3 --- Lowest Achievable Delays --- p.53 / Chapter 4.5.4 --- Results on New Benchmarks --- p.53 / Chapter 4.5.5 --- Simulation Results --- p.55 / Chapter 5 --- Efficient Partitioning-based Extension --- p.57 / Chapter 5.1 --- Introduction --- p.57 / Chapter 5.2 --- Partition-based Extension --- p.58 / Chapter 5.3 --- Experimental Results --- p.61 / Chapter 5.3.1 --- Experiment Setup --- p.61 / Chapter 5.3.2 --- Running Time Improvement with Partitioning Technique --- p.61 / Chapter 6 --- Conclusion --- p.63 / Bibliography --- p.65

Automatic synthesis of digital VLSI layout has been available for many years. It has become a necessary part of the design industry as the window of time from conception to production shrinks with ever increasing competition. However, automatic synthesis of analog VLSI layout remains rare. With digital circuits, there is often room for signal drift. In a digital circuit, a signal can drift within a range before hitting the threshold which triggers a change in logic state. The effect of parasitic capacitances for the most part, hinders the timing margins of the signal, but not its functionality. The logic functionality is protected by the inherent noise immunity of digital circuits. With analog circuits, however, there is little room for drift. Parasitic influence directly affects signal integrity and the functionality of the circuit. The underlying problem automatic VLSI layout programs face is how to minimize this influence. This thesis describes a software tool that was written to show that the minimization of parasitic influence is possible in the case of automatic layout of continuous-time filters using transconductance-capacitor methods.

Includes bibliography.

Bibliography: leaves 302-320 / xiv, iii, 320 leaves : ill ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Thesis (Ph.D.)--University of Adelaide, Faculty of Engineering, 1994?