In the early 1990's, with the boom of the Internet and the advancements in telecommunications, the demand for high-speed communications systems has reached every corner of the world in forms such as, phone exchanges, the internet servers, routers, and all other types of telecommunication systems. These communication systems demand more data computing, storage, and retrieval capabilities at higher speeds, these demands place a great strain on the power system. To lessen this strain, the existing power architecture must be optimized. With the arrival of the age of high speed and power hungry microprocessors, the point of load converter has become a necessity. The power delivery architecture has changed from a centralized distribution box delivering an entire system's power to a distributed architecture, in which a common DC bus voltage is distributed and further converted down at the point of load. Two common distributed bus voltages are 12 V for desktop computers and 48 V for telecommunications server applications. As industry strives to design more functionality into each circuit or motherboard, the area available for the point of load converter is continually decreasing. To meet industries demands of more power in smaller sizes power supply designers must increase the converter's switching frequencies. Unfortunately, as the converter switching frequency increases the efficiency is compromised. In particular, the switching, gate drive and body diode related losses proportionally increase with the switching frequency. This thesis introduces a loss saving self-driven method to drive the secondary side synchronous rectifiers. The loss saving self-driven method introduces two additional transformers that increase the overall footprint of the converter. Also, this thesis proposes a new magnetic integration method to eliminate the need for the two additional gate driver magnetic cores by allowing three discrete power signals to pass through one single magnetic structure. The magnetic integration reduces the overall converter footprint. / Master of Science

Le standard LTE permet l’accès au très haut débit mobile et évolue afind’adresser les applications embarquées de type objets connectés. Mais dans la perspectived’un émetteur-récepteur LTE fabriqué dans une technologie CMOS faible-coût ethautement intégrable, l’amplificateur de puissance (PA) reste le seul bloc actif non intégréà ce jour. De plus, l’utilisation de modulations en quadrature oblige la conceptiond’amplificateurs très linéaires, générant une consommation statique plus importante.Dans ce contexte, ces travaux de thèse portent sur la recherche de composants etde circuits permettant d’atteindre de fortes puissances de sortie et de résoudre le compromisentre la linéarité et la consommation du PA. Deux axes de travail sont identifiéset développés dans cette thèse. Le premier axe porte sur l’utilisation d’un transistor depuissance intégrable en technologie CMOS. Trois cellules de puissance basées sur ce composantsont présentées, de l’étude théorique aux résultats de mesure. Dans le second axede recherche, ce transistor est intégré dans une architecture avancée de PA entièrementréalisée en CMOS. Une méthode de conception de transformateurs intégrés est égalementdéveloppée. Le PA proposé est reconfigurable pour adresser les différents besoinsimposés par le standard LTE : puissance de sortie, haute linéarité et faible consommation. / The LTE standard has been intended for mobile communications. Focusingnot only on higher data rate, LTE now aims at an implementation for the Internetof Things (IoT). The main challenge, in the perspective of a LTE front-end fully manufacturedin a low-cost and high integration level CMOS technology, remains the design ofpower amplifiers (PA). Furthermore, the use of complex quadrature modulation resultsin stringent linearity requirements resulting in an important quiescent dc consumption.In this context, this work focuses on the research of devices and circuits generatinghigh output power and solving the compromise between linearity and consumption ofthe PA. Two strands of work are identified and developed in this thesis. The first oneuses a power transistor available in CMOS technology. Three power cells based on thisdevice are proposed, with detailed theoretical and experimental results. In the secondone, this transistor is then used in a fully-integrated CMOS PA. A design methodologyfor integrated transformers is also presented. The proposed fully-integrated PA is reconfigurablein order to address the main LTE challenges : output power, high linearity andlow consumption.