The objective of this thesis is to introduce an alternative temperature sensor in CMOS technology with small area, low power consumption, and high resolution that can be easily interfaced. A novel temperature sensor utilizing the interface–trap charge pumping phenomenon and the temperature sensitivity of generation current is proposed. This thesis presents the design and characterization of the proposed temperature sensor fabricated in 0.18µm CMOS technology. The prototype sensor is characterized for the temperature range of 27oC–120oC. It has frequency output and exhibits linear transfer characteristics, high sensitivity, and high resolution. This temperature sensor is proposed for microprocessor thermal management applications.

Doctor of Philosophy / Department of Chemical Engineering / James H. Edgar / The integration of high-κ dielectrics with silicon and III-V semiconductors is important due to the need for high speed and high power electronic devices. The purpose of this research was to find the best conditions for fabricating high-κ dielectrics (oxides) on GaN or Si. In particular high-κ oxides can sustain the high breakdown electric field of GaN and utilize the excellent properties of GaN. This research developed an understanding of how process conditions impact the properties of high-κ dielectric on Si and GaN. Thermal and plasma-assisted atomic layer deposition (ALD) was employed to deposit TiO₂ on Si and Al₂O₃ on polar (c-plane) GaN at optimized temperatures of 200°C and 280°C respectively. The semiconductor surface treatment before ALD and the deposition temperature have a strong impact on the dielectric’s electrical properties, surface morphology, stoichiometry, and impurity concentration. Of several etches considered, cleaning the GaN with a piranha etch produced Al₂O₃/GaN MOS capacitors with the best electrical characteristics. The benefits of growing a native oxide of GaN by dry thermal oxidation before depositing the high-κ dielectric was also investigated; oxidizing at 850°C for 30 minutes resulted in the best dielectric-semiconductor interface quality. Interest in nonpolar (m-plane) GaN (due to its lack of strong polarization field) motivated an investigation into the temperature behavior of Al₂O₃/m-plane GaN MOS capacitors. Nonpolar GaN MOS capacitors exhibited a stable flatband voltage across the measured temperature range and demonstrated temperature-stable operation.

abstract: In very small electronic devices the alternate capture and emission of carriers at an individual defect site located at the interface of Si:SiO2 of a MOSFET generates discrete switching in the device conductance referred to as a random telegraph signal (RTS) or random telegraph noise (RTN). In this research work, the integration of random defects positioned across the channel at the Si:SiO2 interface from source end to the drain end in the presence of different random dopant distributions are used to conduct Ensemble Monte-Carlo ( EMC ) based numerical simulation of key device performance metrics for 45 nm gate length MOSFET device. The two main performance parameters that affect RTS based reliability measurements are percentage change in threshold voltage and percentage change in drain current fluctuation in the saturation region. It has been observed as a result of the simulation that changes in both and values moderately decrease as the defect position is gradually moved from source end to the drain end of the channel. Precise analytical device physics based model needs to be developed to explain and assess the EMC simulation based higher VT fluctuations as experienced for trap positions at the source side. A new analytical model has been developed that simultaneously takes account of dopant number variations in the channel and depletion region underneath and carrier mobility fluctuations resulting from fluctuations in surface potential barriers. Comparisons of this new analytical model along with existing analytical models are shown to correlate with 3D EMC simulation based model for assessment of VT fluctuations percentage induced by a single interface trap. With scaling of devices beyond 32 nm node, halo doping at the source and drain are routinely incorporated to combat the threshold voltage roll-off that takes place with effective channel length reduction. As a final study on this regard, 3D EMC simulation method based computations of threshold voltage fluctuations have been performed for varying source and drain halo pocket length to illustrate the threshold voltage fluctuations related reliability problems that have been aggravated by trap positions near the source at the interface compared to conventional 45 nm MOSFET. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

Le rendement consommation/fréquence des futures générations de circuits intégrés sur silicium n’est pas satisfaisant à cause de la faible mobilité électronique de ce semi-conducteur et des relativement grandes tensions d’alimentation VDD requises. Ce travail se propose d’explorer numériquement les potentialités des transistors à effet de champ (FET) à base de matériaux III-V à faible bande interdite et à haute mobilité pour un fonctionnement en haute fréquence et une ultra basse consommation. Tout d’abord, l’étude consiste à analyser théoriquement le fonctionnement d’une capacité MOS III-V en résolvant de façon auto-cohérente les équations de Poisson et Schrödinger (PS). On peut ainsi comprendre comment et pourquoi les effets extrinsèques comme les états de pièges à l’interface high-k/III-V dégradent les caractéristiques intrinsèques. Pour une géométrie 2D, les performances des dispositifs sont estimées pour des applications logiques et analogiques à l’aide d’un modèle de transport quasi-balistique.Nous avons ensuite étudié plus en détails les performances des MOSFET III-V en régimes statiques et dynamiques sous faible VDD, à l’aide du simulateur particulaire MONACO de type Monte Carlo. Les caractéristiques de quatre topologies de MOSFET ont été quantitativement étudiées, en termes de transport quasi-balistique, de courants statiques aux états passants et bloqués, de rendement fréquence/consommation et de bruit. Nous en tirons des conclusions sur l’optimisation de ces dispositifs. Enfin, l'étude comparative avec un FET à base de Si démontre clairement le potentiel des MOSFET III-V pour les applications à haute fréquence, à faible puissance de consommation et à faible bruit. / The optimal frequency performance/power-consumption trade-off is very difficult to achieve using CMOS technology because of low Si carrier mobility and relatively large supply voltage (VDD) required for circuit operation. The main objective of this work is to theoretically explore, in terms of operation frequency and power consumption, the potentialities of nano-MOSFET based on III-V materials with low energy bandgap and high electron mobility.First, this work analyzes theoretically the operation of a III-V MOS capacitor using self-consistent solution of Poisson - Schrödinger system equation. We can thus understand how and why the interface trap state densities at high-k/III-V interfaces degrade the intrinsic characteristics. For a 2D geometry, the performance of devices is estimated for digital and analog applications using a model of quasi-ballistic transport.Then, we estimated the performance of III-V MOSFET in static and dynamic regimes under low VDD, using MONACO a Monte Carlo simulator. The characteristics of four designs of III-V MOSFET have been studied quantitatively in terms of quasi-ballistic transport, DC current in ON and OFF states, frequency/consumption efficiency and optimum matching conditions of noise. We provide the guideline on the design optimization of the devices.Finally, the comparative study with Si-based devices clearly demonstrates the potentiality of III-V nano-MOSFET architectures for high-frequency and low-noise application under low operating power and even for low voltage logic.