Abstract The purpose of this thesis is to study the electrical characteristics of ultra-thin high-k gate oxide-semiconductor interfaces. The measured samples are Y2O3/Si¡BGd2O3/GaAs¡BGa2O3(Gd2O3)/GaAs MOS capacitors. An accurate C-V relation has been obtained consistently by using a model that includes both series and shunt parasitic resistances. Using the semiconductor parameters and the oxide parameters, an ideal C-V curve with Dit = 0 is fitted to the accurate capacitance data, and the interface state density is deduced by Terman method. After post - metallization annealing (PMA) at 425¢J, the oxide charge density, interface state density and leakage current were reduced. The results are following : (1) For Y2O3/Si MOS capacitors, we obtained a oxide charge density ~ 7.7 x 1010 cm-2, an interface state density ~ 3.6 x 1010 cm-2ev-1, and an equivalent oxide thickness ~ 52Å; (2) For Gd2O3/GaAs MOS capacitors, we obtained a oxide charge density ~ 9.8 x 1011 cm-2, an interface state density ~ 2 x 1011 cm-2ev-1, and an equivalent oxide thickness ~ 57Å; (3) For Ga2O3(Gd2O3)/GaAs MOS capacitors, we obtained a oxide charge density ~ 4.2 x 1012 cm-2, an interface state density ~ 6 x 1011 cm-2ev-1, and an equivalent oxide thickness ~ 91Å. The dielectric constants obtained from our data are smaller than the reported values. A possible explanation is that an interfacial layer formed at the oxide/semiconductor interface to reduce equivalent dielectric constant.

abstract: Total dose sensing systems (or radiation detection systems) have many applications, ranging from survey monitors used to supervise the generated radioactive waste at nuclear power plants to personal dosimeters which measure the radiation dose accumulated in individuals. This dissertation work will present two different types of novel devices developed at Arizona State University for total dose sensing applications. The first detector technology is a mechanically flexible metal-chalcogenide glass (ChG) based system which is fabricated on low cost substrates and are intended as disposable total dose sensors. Compared to existing commercial technologies, these thin film radiation sensors are simpler in form and function, and cheaper to produce and operate. The sensors measure dose through resistance change and are suitable for applications such as reactor dosimetry, radiation chemistry, and clinical dosimetry. They are ideal for wearable devices due to the lightweight construction, inherent robustness to resist breaking when mechanically stressed, and ability to attach to non-flat objects. Moreover, their performance can be easily controlled by tuning design variables and changing incorporated materials. The second detector technology is a wireless dosimeter intended for remote total dose sensing. They are based on a capacitively loaded folded patch antenna resonating in the range of 3 GHz to 8 GHz for which the load capacitance varies as a function of total dose. The dosimeter does not need power to operate thus enabling its use and implementation in the field without requiring a battery for its read-out. As a result, the dosimeter is suitable for applications such as unattended detection systems destined for covert monitoring of merchandise crossing borders, where nuclear material tracking is a concern. The sensitive element can be any device exhibiting a known variation of capacitance with total ionizing dose. The sensitivity of the dosimeter is related to the capacitance variation of the radiation sensitive device as well as the high frequency system used for reading. Both technologies come with the advantage that they are easy to manufacture with reasonably low cost and sensing can be readily read-out. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Neste trabalho foram fabricados e caracterizados eletricamente capacitores MOS com óxido de silício ultrafino (2,6 nm) com porta de silício policristalino (Si-poli) P+ e N+. Os capacitores MOS com porta de Si-poli dopados com boro tiveram a estrutura Si-poli/SiO2/Si previamente implantada com nitrogênio nas doses de 1.10\'POT.13\', 1.10\'POT.14\', 1.10\'POT.15\' e 5.10\'POT.15\' at.cm-², com o pico da concentração de nitrogênio próximo à interface SiO2/Si. Os capacitores MOS foram fabricados sobre lâminas de silício do tipo p que passaram por uma limpeza química préoxidação tipo RCA mais imersão final em solução diluída em HF. Na seqüência, as lâminas foram oxidadas em um ambiente de O2 (1,5 l/min) + N2/H2 (2l/min; 10 %) que proporcionou óxidos de silício com excelentes características elétricas. Para a fabricação dos capacitores MOS com porta de Si-poli P+, utilizou-se SOG de boro seguido por difusão térmica sobre camada de Si-poli (340 nm). Após testes com receitas de difusão a 950, 1000, 1050 e 1100 °C todas padronizadas por um tempo de 30 min optamos por realizar a difusão a 1050 °C por 30 min, pois essa receita proporcionou concentração de boro superior a 1.10\'POT.20\' at.cm-³ e segregação desprezível do boro em direção ao substrato de Si. A dopagem dos capacitores MOS com porta de Si-poli N+ foi realizada por aplicação do SOG de fósforo seguido por difusão a 1050 °C por 30 min. Os resultados indicaram segregação do boro desprezível para o Si, baixa densidade de estados de interface (< 1.10\'POT.11\' eV-¹ cm-²) e no aumento do campo elétrico de ruptura (de 14 MV/cm para 21 MV/cm) com o aumento da dose de nitrogênio (de 1.10\'POT.13\' a 5.10\'POT.15\' at/cm²). Embora ocorresse uma maior dispersão e um aumento desfavorável da tensão de banda plana com o aumento da dose de nitrogênio, os valores 1.10\'POT.15\' e 5.10\'POT.15\' at.cm-² resultaram em capacitores MOS com tensão de faixa plana próxima ao parâmetro diferença de função trabalho (\'fi\' MS) significando densidade efetiva de cargas no dielétrico de porta inferior à cerca de 1.10\'POT.11\' cm-². / In this work we manufactured and electrically characterized MOS capacitors with ultrathin silicon oxides (2,6 nm) and polysilicon gate (Si-poli), P+ or N+. P+ - doped polysilicon gate MOS capacitors (Si-poli/SiO2/Si structure) were previously implanted with nitrogen using doses of 1.10\'POT.13\', 1.10\'POT.14\', 1.10\'POT.15\' and 5.10\'POT.15\' at.cm-², and implantation peak centered close to the SiO2/Si interface before boron doping. The MOS capacitors were fabricated on p-type silicon wafers, which were submitted to RCA - based cleaning procedure and a final dip in diluted HF solution. Following, the wafers were oxidize in ultrapure O2 (1,5 l/min) + N2/H2 (2l/min; 10 %) having, as a result, silicon gate oxides with excellent electrical characteristics. To obtain P+ polysilicon, it Spin On Glass (SOG) of boron the wafers was annealed at 950, 1000, 1050 or 1100 °C during 30 min. We have chosen a diffusion recipe of 1050 °C during 30 min to obtain volumetric concentration of boron higher than 1.10\'POT.20\' cm-³ and no boron segregation to the silicon. N+ polysilicon was also obtained using phosphorus SOG and diffusion at 1050 °C during 30 min. As a result, besides no boron segregation to Si, the interface states density was low (< 1.10\'POT.11\' eV-¹cm-²) and the breakdown field of the gate oxides increased (from 14 MV/cm to 21 MV/cm) by increasing the nitrogen doses (from 1.10\'POT.13\' to 5.10\'POT.15\' at/cm²). Although a larger dispersion and increasing of the flat-band voltage have occurred as the nitrogen dose was increased, values of 1.10\'POT.15\' and 5.10\'POT.15\' at.cm-² induced flat band voltage close to the parameter workfunction difference (\'fi\'MS) which meant effective charge density in the gate dielectrics lower than about 1.10\'POT.11\' cm-².

Neste trabalho foram fabricados e caracterizados capacitores MOS com camada dielétrica de oxinitreto de silício de diferentes composição química, depositada pela técnica de PECVD a baixa temperatura, com o intuito de estudar suas propriedades dielétricas e de interface visando à aplicação deste material em dispositivos MOS e de filme fino. Os capacitores foram fabricados sobre lâminas de silício do tipo p que passaram pelo processo de limpeza química inicial, seguida da deposição da camada dielétrica, fotogravação, metalização e sinterização. Os filmes de SiOxNy, utilizados como camada dielétrica, foram depositados pela técnica de PECVD à temperatura de 320ºC variando os fluxos dos gases precursores de forma a obter filmes com diferentes composições químicas. Os capacitores MOS foram caracterizados por medidas de capacitância e corrente em função da tensão, de onde foram extraídas a densidade de estados de interface, a densidade de carga efetiva, constante dielétrica e campo elétrico de ruptura dos filmes. Os resultados mostraram uma variação linear da constante dielétrica do filme em função da concentração de nitrogênio, indo do valor de 3,9, correspondente ao dióxido de silício estequiométrico (SiO2) à 7,2 correspondente ao nitreto de silício estequiométrico (Si3N4). Também observamos que o nitrogênio é uma barreira eficiente à difusão de impurezas através do dielétrico. Porém, notamos uma grande dispersão de duas ordens de grandeza nos valores da carga efetiva (Nss) e de densidade de estados de interface (Dit). Por outro lado, controlando algumas variáveis de forma a manter constante o valor de Nss ( ~1012 cm-2), observamos uma variação de Dit em função da concentração de nitrogênio no filme, esta variação porém é pequena comparada com a dispersão de duas ordens de grandeza observada, que atribuímos assim a fatores externos. O menor valor obtido de Dit foi de 4,55.1010 eV-1.cm-2, que é ótimo para um filme obtido por PECVD, sem nenhum tratamento térmico e melhor que os reportados na literatura para dielétricos obtidos por técnicas que utilizam altas temperaturas (LPCVD-800ºC e oxinitretação térmica – 1100ºC). Assim, podemos concluir que a técnica de PECVD é promissora para a obtenção de dielétricos a baixas temperaturas. / In this work, MOS capacitors with different chemical composition silicon oxynitride insulating layer, deposited by PECVD technique at low temperature were fabricated and characterized, in order to study its dielectric and interface properties, seeking its aplication as insulating layer in MOS and thin films devices. The MOS capacitors were fabricated onto p-silicion wafers previously cleaned by a standard process, followed by the insulating layer deposition, photolitography, metalization and sinterization. The SiOxNy insulating layer was deposited by the PECVD technique at 320ºC changing the precursor gases flows to obtain films with different chemical compositions. The MOS capacitors were characterized by capacitance and current vs. voltage measurements, from where the interface state density (Dit), the effective charge density (Nss), the dielectric constant (k) and the film electrical breakdown field (Ebd) were extracted. The results showed a dielectric constant varying linearly as a function of the films nitrogen concentration, going from a value of 3.9, corresponding to stoichiometric silicon dioxide (SiO2) to a value of 7.2, corresponding to stoichiometric silicon nitride film (Si3N4). We also observed that nitrogen is an efficient diffusion barrier against contaminants. However, a large dispersion, about two orders of magnitude, in the effective charge and in the interface state density was observed. On the other hand, controlling some variables so as to keep the Nss value constant (~1012 cm-2) we observed a Dit variation as a function of the film nitrogen concentration, this variation is small when compared with the observed dispersion of two orders of magnitude, thus attributed to external factors. The smallest obtained Dit was 4.55.1010 eV-1.cm-2, which is unexpected for a PECVD film without any anealing process and is better than the values reported in the literature for dielectrics obtained at high temperatures techniques (as LPCVD – 800ºC and thermal oxynitridation – 1100ºC). Therefore, we can conclude that the PECVD technique is promising for obtaining low temperature dielectrics.

Neste trabalho foram fabricados e caracterizados capacitores MOS com camada dielétrica de oxinitreto de silício de diferentes composição química, depositada pela técnica de PECVD a baixa temperatura, com o intuito de estudar suas propriedades dielétricas e de interface visando à aplicação deste material em dispositivos MOS e de filme fino. Os capacitores foram fabricados sobre lâminas de silício do tipo p que passaram pelo processo de limpeza química inicial, seguida da deposição da camada dielétrica, fotogravação, metalização e sinterização. Os filmes de SiOxNy, utilizados como camada dielétrica, foram depositados pela técnica de PECVD à temperatura de 320ºC variando os fluxos dos gases precursores de forma a obter filmes com diferentes composições químicas. Os capacitores MOS foram caracterizados por medidas de capacitância e corrente em função da tensão, de onde foram extraídas a densidade de estados de interface, a densidade de carga efetiva, constante dielétrica e campo elétrico de ruptura dos filmes. Os resultados mostraram uma variação linear da constante dielétrica do filme em função da concentração de nitrogênio, indo do valor de 3,9, correspondente ao dióxido de silício estequiométrico (SiO2) à 7,2 correspondente ao nitreto de silício estequiométrico (Si3N4). Também observamos que o nitrogênio é uma barreira eficiente à difusão de impurezas através do dielétrico. Porém, notamos uma grande dispersão de duas ordens de grandeza nos valores da carga efetiva (Nss) e de densidade de estados de interface (Dit). Por outro lado, controlando algumas variáveis de forma a manter constante o valor de Nss ( ~1012 cm-2), observamos uma variação de Dit em função da concentração de nitrogênio no filme, esta variação porém é pequena comparada com a dispersão de duas ordens de grandeza observada, que atribuímos assim a fatores externos. O menor valor obtido de Dit foi de 4,55.1010 eV-1.cm-2, que é ótimo para um filme obtido por PECVD, sem nenhum tratamento térmico e melhor que os reportados na literatura para dielétricos obtidos por técnicas que utilizam altas temperaturas (LPCVD-800ºC e oxinitretação térmica – 1100ºC). Assim, podemos concluir que a técnica de PECVD é promissora para a obtenção de dielétricos a baixas temperaturas. / In this work, MOS capacitors with different chemical composition silicon oxynitride insulating layer, deposited by PECVD technique at low temperature were fabricated and characterized, in order to study its dielectric and interface properties, seeking its aplication as insulating layer in MOS and thin films devices. The MOS capacitors were fabricated onto p-silicion wafers previously cleaned by a standard process, followed by the insulating layer deposition, photolitography, metalization and sinterization. The SiOxNy insulating layer was deposited by the PECVD technique at 320ºC changing the precursor gases flows to obtain films with different chemical compositions. The MOS capacitors were characterized by capacitance and current vs. voltage measurements, from where the interface state density (Dit), the effective charge density (Nss), the dielectric constant (k) and the film electrical breakdown field (Ebd) were extracted. The results showed a dielectric constant varying linearly as a function of the films nitrogen concentration, going from a value of 3.9, corresponding to stoichiometric silicon dioxide (SiO2) to a value of 7.2, corresponding to stoichiometric silicon nitride film (Si3N4). We also observed that nitrogen is an efficient diffusion barrier against contaminants. However, a large dispersion, about two orders of magnitude, in the effective charge and in the interface state density was observed. On the other hand, controlling some variables so as to keep the Nss value constant (~1012 cm-2) we observed a Dit variation as a function of the film nitrogen concentration, this variation is small when compared with the observed dispersion of two orders of magnitude, thus attributed to external factors. The smallest obtained Dit was 4.55.1010 eV-1.cm-2, which is unexpected for a PECVD film without any anealing process and is better than the values reported in the literature for dielectrics obtained at high temperatures techniques (as LPCVD – 800ºC and thermal oxynitridation – 1100ºC). Therefore, we can conclude that the PECVD technique is promising for obtaining low temperature dielectrics.

Neste trabalho foram fabricados e caracterizados eletricamente capacitores MOS com óxido de silício ultrafino (2,6 nm) com porta de silício policristalino (Si-poli) P+ e N+. Os capacitores MOS com porta de Si-poli dopados com boro tiveram a estrutura Si-poli/SiO2/Si previamente implantada com nitrogênio nas doses de 1.10\'POT.13\', 1.10\'POT.14\', 1.10\'POT.15\' e 5.10\'POT.15\' at.cm-², com o pico da concentração de nitrogênio próximo à interface SiO2/Si. Os capacitores MOS foram fabricados sobre lâminas de silício do tipo p que passaram por uma limpeza química préoxidação tipo RCA mais imersão final em solução diluída em HF. Na seqüência, as lâminas foram oxidadas em um ambiente de O2 (1,5 l/min) + N2/H2 (2l/min; 10 %) que proporcionou óxidos de silício com excelentes características elétricas. Para a fabricação dos capacitores MOS com porta de Si-poli P+, utilizou-se SOG de boro seguido por difusão térmica sobre camada de Si-poli (340 nm). Após testes com receitas de difusão a 950, 1000, 1050 e 1100 °C todas padronizadas por um tempo de 30 min optamos por realizar a difusão a 1050 °C por 30 min, pois essa receita proporcionou concentração de boro superior a 1.10\'POT.20\' at.cm-³ e segregação desprezível do boro em direção ao substrato de Si. A dopagem dos capacitores MOS com porta de Si-poli N+ foi realizada por aplicação do SOG de fósforo seguido por difusão a 1050 °C por 30 min. Os resultados indicaram segregação do boro desprezível para o Si, baixa densidade de estados de interface (< 1.10\'POT.11\' eV-¹ cm-²) e no aumento do campo elétrico de ruptura (de 14 MV/cm para 21 MV/cm) com o aumento da dose de nitrogênio (de 1.10\'POT.13\' a 5.10\'POT.15\' at/cm²). Embora ocorresse uma maior dispersão e um aumento desfavorável da tensão de banda plana com o aumento da dose de nitrogênio, os valores 1.10\'POT.15\' e 5.10\'POT.15\' at.cm-² resultaram em capacitores MOS com tensão de faixa plana próxima ao parâmetro diferença de função trabalho (\'fi\' MS) significando densidade efetiva de cargas no dielétrico de porta inferior à cerca de 1.10\'POT.11\' cm-². / In this work we manufactured and electrically characterized MOS capacitors with ultrathin silicon oxides (2,6 nm) and polysilicon gate (Si-poli), P+ or N+. P+ - doped polysilicon gate MOS capacitors (Si-poli/SiO2/Si structure) were previously implanted with nitrogen using doses of 1.10\'POT.13\', 1.10\'POT.14\', 1.10\'POT.15\' and 5.10\'POT.15\' at.cm-², and implantation peak centered close to the SiO2/Si interface before boron doping. The MOS capacitors were fabricated on p-type silicon wafers, which were submitted to RCA - based cleaning procedure and a final dip in diluted HF solution. Following, the wafers were oxidize in ultrapure O2 (1,5 l/min) + N2/H2 (2l/min; 10 %) having, as a result, silicon gate oxides with excellent electrical characteristics. To obtain P+ polysilicon, it Spin On Glass (SOG) of boron the wafers was annealed at 950, 1000, 1050 or 1100 °C during 30 min. We have chosen a diffusion recipe of 1050 °C during 30 min to obtain volumetric concentration of boron higher than 1.10\'POT.20\' cm-³ and no boron segregation to the silicon. N+ polysilicon was also obtained using phosphorus SOG and diffusion at 1050 °C during 30 min. As a result, besides no boron segregation to Si, the interface states density was low (< 1.10\'POT.11\' eV-¹cm-²) and the breakdown field of the gate oxides increased (from 14 MV/cm to 21 MV/cm) by increasing the nitrogen doses (from 1.10\'POT.13\' to 5.10\'POT.15\' at/cm²). Although a larger dispersion and increasing of the flat-band voltage have occurred as the nitrogen dose was increased, values of 1.10\'POT.15\' and 5.10\'POT.15\' at.cm-² induced flat band voltage close to the parameter workfunction difference (\'fi\'MS) which meant effective charge density in the gate dielectrics lower than about 1.10\'POT.11\' cm-².

Doctor of Philosophy / Department of Chemical Engineering / James H. Edgar / The integration of high-κ dielectrics with silicon and III-V semiconductors is important due to the need for high speed and high power electronic devices. The purpose of this research was to find the best conditions for fabricating high-κ dielectrics (oxides) on GaN or Si. In particular high-κ oxides can sustain the high breakdown electric field of GaN and utilize the excellent properties of GaN. This research developed an understanding of how process conditions impact the properties of high-κ dielectric on Si and GaN. Thermal and plasma-assisted atomic layer deposition (ALD) was employed to deposit TiO₂ on Si and Al₂O₃ on polar (c-plane) GaN at optimized temperatures of 200°C and 280°C respectively. The semiconductor surface treatment before ALD and the deposition temperature have a strong impact on the dielectric’s electrical properties, surface morphology, stoichiometry, and impurity concentration. Of several etches considered, cleaning the GaN with a piranha etch produced Al₂O₃/GaN MOS capacitors with the best electrical characteristics. The benefits of growing a native oxide of GaN by dry thermal oxidation before depositing the high-κ dielectric was also investigated; oxidizing at 850°C for 30 minutes resulted in the best dielectric-semiconductor interface quality. Interest in nonpolar (m-plane) GaN (due to its lack of strong polarization field) motivated an investigation into the temperature behavior of Al₂O₃/m-plane GaN MOS capacitors. Nonpolar GaN MOS capacitors exhibited a stable flatband voltage across the measured temperature range and demonstrated temperature-stable operation.

La substitution du canal de silicium par un semi-conducteur III-V est une des voies envisagées pour accroitre la mobilité des électrons dans les transistors n-MOSFET et ainsi réduire la consommation des circuits. Afin de réduire les coûts et de profiter des plateformes industrielles de la microélectronique, les transistors III-V doivent être réalisés sur des substrats de silicium. Cependant, la différence de paramètre de maille entre le Si et les couches III-V induit de nombreux défauts cristallins dans le canal du transistor, diminuant la mobilité des porteurs. L’objectif de cette thèse est la réalisation de transistors à canal III-V sur substrat de silicium au sein de la plateforme microélectronique du CEA Leti. Dans le cadre de ces travaux, deux filières technologiques d’intégration ont été développées pour la réalisation de transistors tri-gate à base d’In0,53Ga0,47As sur substrat de silicium : par un collage moléculaire d’une couche d’InGaAs sur InP et par une épitaxie directe de la couche d’InGaAs sur substrat Si. Les différentes étapes technologiques spécifiques à l’InGaAs ont été mises au point au cours de ces travaux, en prenant en compte les contraintes de contamination des équipements. Le traitement de surface de l’InGaAs et le dépôt du diélectrique de grille à haute permittivité (type high-k) par ALD ont été particulièrement étudiés afin de réduire la quantité d’états d’interface (Dit) et d’optimiser l’EOT. Pour cela, des analyses XPS et des mesures électriques C(V) de capacités MOS ont été réalisées à l’échelle d’un substrat de 300mm de diamètre. / The replacement of the silicon channel by III-V materials is investigated to increase the electron mobility in the channel and reduce the power consumption. In order to decrease the cost and to take advantage of the microelectronic silicon platform, III-V transistors must be built on Silicon substrates. However, the lattice parameter mismatch between Silicon and the III-V layers leads to a high defects density in the channel and reduces the carrier mobility. This thesis aims to realize III-V transistors on silicon substrate in the CEA-Leti microelectronic clean room. In the frame of this PhD, two integration process are elaborated to realize In0,53Ga0,47As tri-gate transistors on silicon: the molecular bonding of an InGaAs layer grown on a InP substrate, and the direct epitaxy of InGaAs on a silicon substrate. The fabrication steps for InGaAs transistors were developed, taking into account the clean room contamination restriction. InGaAs surface treatment and high-permittivity dielectric deposition by ALD are studied in order to reduce the density of interface states (Dit) and to optimize the EOT. XPS analysis and C(V) measurement are performed at the scale of a 300mm Silicon substrate.

4H-SiC based Metal-Oxide Semiconductor(MOS) capacitors are promising key components for next generation power devices. For high frequency power applications, however, there is a major drawback of this type of devices, i.e. they have low inversion channel mobility that consequently affects the switching operation in MOS Field-Effect Transistors (MOSFETs). Carbon clusters or excess carbon atoms in the interface between the dielectric layer and SiC is commonly considered to be the carrier trapping and scattering centers that lower the carrier channel mobility. Based on the previous work in the research group, a new fabrication process for forming the dielectric layer with a lower density of the trap states is investigated. The process consists of standard semiconductor cleaning, pre-treatments, pre-oxidation, plasma enhanced chemical vapor deposition (PECVD) and post oxidation annealing. I-V measurements of the dielectric strength showed that the resulting layers can sustain proper working condition under an electric field of at least 5MV/cm. C-V characteristics measurements provided the evidence that the proposed method can effectively reduce the interfacial states, which are main culprit for a large flat band voltage shift of C-V characteristics, in particular under annealing at 900°C in nitrogen atmosphere.

Apresentamos neste trabalho um estudo do efeito da depleção do silício policristalino e da corrente de tunelamento em dispositivos com óxidos de porta finos. Utilizamos curvas características da capacitância em função da tensão de porta (C-V), para analisar a degradação causada por estes efeitos.Quanto ao efeito da depleção do silício policristalino a capacitância total na região de inversão apresenta uma redução conforme a concentração de dopantes do silício policristalino diminui. Este efeito foi observado em curvas C-V tanto de alta como de baixa freqüência, sendo esta última mais afetada. A corrente de tunelamento através do óxido de porta apresentou uma influência na largura da região de depleção no silício, que aumentou devido ao tunelamento de portadores do substrato. Como resultado, uma diminuição na capacitância do silício foi observada, fazendo a curva C-V diminuir na região de inversão. Quando considerado o efeito de depleção no silício policristalino junto com o efeito do tunelamento, observou-se que na região da porta houve um excesso de portadores, causando uma diminuição na região de depleção do silício policristalino. Neste caso a curva C-V sofreu uma maior redução, tornando-se difícil separar os dois efeitos. A curva C-V de baixa freqüência foi a mais atingida, pois como os portadores tem tempo de resposta, pode-se observar a influência da corrente de tunelamento nas cargas de inversão. Apresentamos ainda um novo método para a determinação da concentração de dopantes no substrato e no silício policristalino, através de curvas C-V de alta freqüência. Simulações numéricas bidimensionais e medidas experimentais foram utilizadas para validação do método. Os resultados obtidos indicam que o método proposto apresenta um grande potencial, tendo como principal vantagem a simplicidade de aplicação. / In this work we present the study of polysilicon depletion and the gate tunneling current effects in thin-gate oxide devices. Characteristic curves of capacitance as a function of the gate voltage (C-V) were used to analyze the degradation caused for these effects. Regarding the poly depletion effect, a reduction of the total capacitance in the inversion region was verified as the polysilicon doping concentration decreases. This effect was observed in C-V curves in high and low frequency, being the last one more affected. The gate tunneling current presented an influence on the width of the depletion silicon region, which increased due to the carriers tunneling from the substrate. As a result, a reduction in the silicon capacitance was observed, causing the C-V curve reduction in the inversion region. When the polysilicon depletion effect is considered together with the tunneling effect, it was observed that there is a carriers excess in the gate region, causing a reduction of the polysilicon depletion region width. In this case, the C-V curve suffered a larger reduction, making difficult to separate both effects. The most affected characteristic was the C-V curve at low frequency, due to existence of the carrier response time that allows observing the influence of the tunneling current in inversion charges. A new method for the determination of the doping concentration of substrate and polysilicon was also presented, through C-V curves at high frequency. Two-dimensional simulations and experimental measurements were used to validate the method. The obtained results indicate that the propose method present a higher potential, having as principal advantage the simplicity of application.