In recent years, both hafnia and zirconia have been looked at closely in the quest for a high permittivity gate dielectric to replace silicon dioxide in advanced metal oxide semiconductor field effect transistors (MOSFET). Hafnium dioxide or HfO2 is chosen for its high dielectric constant (five times that of SiO2) and compatibility with stringent requirements of the Si process. As deposited, thin hafnia films are typically amorphous but turn polycrystalline after a post-deposition anneal. To control the phase composition in hafnia films understanding of structural phase transitions is a first step. In this dissertation using first principles methods we consider three phase transitions of hafnia and zirconia: monoclinic to tetragonal, tetragonal to cubic and amorphous to crystalline. Because the high surface to volume ratio in hafnia films and powders plays an important role in phase transitions, we also study the surface properties of hafnia. We discuss the mechanisms of various phase transitions and theoretically estimate the transition temperatures. We find two types of amorphous hafnia and show that they have different structural and electronic properties. The small energy barrier between the amorphous and crystalline structures is found to cause the low crystallization temperature. Moreover, we calculate work functions and surface energies for hafnia surfaces and show the surface suppression of the phase transitions. / text

Hafnium and Zirconium based gate dielectrics are considered potential candidates to replace SiO2 or SiON as the gate dielectric in CMOS processing. Furthermore, the addition of nitrogen into this pseudo-binary alloy has been shown to improve their thermal stability, electrical properties, and reduce dopant penetration. Because CMOS processing requires high temperature anneals (up to 1050 °C), it is important to understand the diffusion properties of any metal associated with the gate dielectric in silicon at these temperatures. In addition, dopant penetration from the doped polysilicon gate into the Si channel at these temperatures must also be studied. Impurity outdiffusion (Hf, Zr) from the dielectric, or dopant (B, As, P) penetration through the dielectric into the channel region would likely result in deleterious effects upon the carrier mobility. In this dissertation extensive thermal stability studies of alternate gate dielectric candidates ZrSixOy and HfSixOy are presented. Dopant penetration studies from doped-polysilicon through HfSixOy and HfSixOyNz are also presented. Rutherford backscattering spectroscopy (RBS), heavy ion RBS (HI-RBS), x-ray photoelectron spectroscopy (XPS), high resolution transmission electron microscopy (HR-TEM), and time of flight and dynamic secondary ion mass spectroscopy (ToF-SIMS, D-SIMS) methods were used to characterize these materials. The dopant diffusivity is calculated by modeling of the dopant profiles in the Si substrate. In this disseration is reported that Hf silicate films are more stable than Zr silicate films, from the metal interdiffusion point of view. On the other hand, dopant (B, As, and P) penetration is observed for HfSixOy films. However, the addition of nitrogen to the Hf - Si - O systems improves the dopant penetration properties of the resulting HfSixOyNz films.

Neste trabalho foram fabricados e caracterizados eletricamente capacitores MOS com óxido de silício ultrafino (2,6 nm) com porta de silício policristalino (Si-poli) P+ e N+. Os capacitores MOS com porta de Si-poli dopados com boro tiveram a estrutura Si-poli/SiO2/Si previamente implantada com nitrogênio nas doses de 1.10\'POT.13\', 1.10\'POT.14\', 1.10\'POT.15\' e 5.10\'POT.15\' at.cm-², com o pico da concentração de nitrogênio próximo à interface SiO2/Si. Os capacitores MOS foram fabricados sobre lâminas de silício do tipo p que passaram por uma limpeza química préoxidação tipo RCA mais imersão final em solução diluída em HF. Na seqüência, as lâminas foram oxidadas em um ambiente de O2 (1,5 l/min) + N2/H2 (2l/min; 10 %) que proporcionou óxidos de silício com excelentes características elétricas. Para a fabricação dos capacitores MOS com porta de Si-poli P+, utilizou-se SOG de boro seguido por difusão térmica sobre camada de Si-poli (340 nm). Após testes com receitas de difusão a 950, 1000, 1050 e 1100 °C todas padronizadas por um tempo de 30 min optamos por realizar a difusão a 1050 °C por 30 min, pois essa receita proporcionou concentração de boro superior a 1.10\'POT.20\' at.cm-³ e segregação desprezível do boro em direção ao substrato de Si. A dopagem dos capacitores MOS com porta de Si-poli N+ foi realizada por aplicação do SOG de fósforo seguido por difusão a 1050 °C por 30 min. Os resultados indicaram segregação do boro desprezível para o Si, baixa densidade de estados de interface (< 1.10\'POT.11\' eV-¹ cm-²) e no aumento do campo elétrico de ruptura (de 14 MV/cm para 21 MV/cm) com o aumento da dose de nitrogênio (de 1.10\'POT.13\' a 5.10\'POT.15\' at/cm²). Embora ocorresse uma maior dispersão e um aumento desfavorável da tensão de banda plana com o aumento da dose de nitrogênio, os valores 1.10\'POT.15\' e 5.10\'POT.15\' at.cm-² resultaram em capacitores MOS com tensão de faixa plana próxima ao parâmetro diferença de função trabalho (\'fi\' MS) significando densidade efetiva de cargas no dielétrico de porta inferior à cerca de 1.10\'POT.11\' cm-². / In this work we manufactured and electrically characterized MOS capacitors with ultrathin silicon oxides (2,6 nm) and polysilicon gate (Si-poli), P+ or N+. P+ - doped polysilicon gate MOS capacitors (Si-poli/SiO2/Si structure) were previously implanted with nitrogen using doses of 1.10\'POT.13\', 1.10\'POT.14\', 1.10\'POT.15\' and 5.10\'POT.15\' at.cm-², and implantation peak centered close to the SiO2/Si interface before boron doping. The MOS capacitors were fabricated on p-type silicon wafers, which were submitted to RCA - based cleaning procedure and a final dip in diluted HF solution. Following, the wafers were oxidize in ultrapure O2 (1,5 l/min) + N2/H2 (2l/min; 10 %) having, as a result, silicon gate oxides with excellent electrical characteristics. To obtain P+ polysilicon, it Spin On Glass (SOG) of boron the wafers was annealed at 950, 1000, 1050 or 1100 °C during 30 min. We have chosen a diffusion recipe of 1050 °C during 30 min to obtain volumetric concentration of boron higher than 1.10\'POT.20\' cm-³ and no boron segregation to the silicon. N+ polysilicon was also obtained using phosphorus SOG and diffusion at 1050 °C during 30 min. As a result, besides no boron segregation to Si, the interface states density was low (< 1.10\'POT.11\' eV-¹cm-²) and the breakdown field of the gate oxides increased (from 14 MV/cm to 21 MV/cm) by increasing the nitrogen doses (from 1.10\'POT.13\' to 5.10\'POT.15\' at/cm²). Although a larger dispersion and increasing of the flat-band voltage have occurred as the nitrogen dose was increased, values of 1.10\'POT.15\' and 5.10\'POT.15\' at.cm-² induced flat band voltage close to the parameter workfunction difference (\'fi\'MS) which meant effective charge density in the gate dielectrics lower than about 1.10\'POT.11\' cm-².

Neste trabalho foram fabricados e caracterizados eletricamente capacitores MOS com óxido de silício ultrafino (2,6 nm) com porta de silício policristalino (Si-poli) P+ e N+. Os capacitores MOS com porta de Si-poli dopados com boro tiveram a estrutura Si-poli/SiO2/Si previamente implantada com nitrogênio nas doses de 1.10\'POT.13\', 1.10\'POT.14\', 1.10\'POT.15\' e 5.10\'POT.15\' at.cm-², com o pico da concentração de nitrogênio próximo à interface SiO2/Si. Os capacitores MOS foram fabricados sobre lâminas de silício do tipo p que passaram por uma limpeza química préoxidação tipo RCA mais imersão final em solução diluída em HF. Na seqüência, as lâminas foram oxidadas em um ambiente de O2 (1,5 l/min) + N2/H2 (2l/min; 10 %) que proporcionou óxidos de silício com excelentes características elétricas. Para a fabricação dos capacitores MOS com porta de Si-poli P+, utilizou-se SOG de boro seguido por difusão térmica sobre camada de Si-poli (340 nm). Após testes com receitas de difusão a 950, 1000, 1050 e 1100 °C todas padronizadas por um tempo de 30 min optamos por realizar a difusão a 1050 °C por 30 min, pois essa receita proporcionou concentração de boro superior a 1.10\'POT.20\' at.cm-³ e segregação desprezível do boro em direção ao substrato de Si. A dopagem dos capacitores MOS com porta de Si-poli N+ foi realizada por aplicação do SOG de fósforo seguido por difusão a 1050 °C por 30 min. Os resultados indicaram segregação do boro desprezível para o Si, baixa densidade de estados de interface (< 1.10\'POT.11\' eV-¹ cm-²) e no aumento do campo elétrico de ruptura (de 14 MV/cm para 21 MV/cm) com o aumento da dose de nitrogênio (de 1.10\'POT.13\' a 5.10\'POT.15\' at/cm²). Embora ocorresse uma maior dispersão e um aumento desfavorável da tensão de banda plana com o aumento da dose de nitrogênio, os valores 1.10\'POT.15\' e 5.10\'POT.15\' at.cm-² resultaram em capacitores MOS com tensão de faixa plana próxima ao parâmetro diferença de função trabalho (\'fi\' MS) significando densidade efetiva de cargas no dielétrico de porta inferior à cerca de 1.10\'POT.11\' cm-². / In this work we manufactured and electrically characterized MOS capacitors with ultrathin silicon oxides (2,6 nm) and polysilicon gate (Si-poli), P+ or N+. P+ - doped polysilicon gate MOS capacitors (Si-poli/SiO2/Si structure) were previously implanted with nitrogen using doses of 1.10\'POT.13\', 1.10\'POT.14\', 1.10\'POT.15\' and 5.10\'POT.15\' at.cm-², and implantation peak centered close to the SiO2/Si interface before boron doping. The MOS capacitors were fabricated on p-type silicon wafers, which were submitted to RCA - based cleaning procedure and a final dip in diluted HF solution. Following, the wafers were oxidize in ultrapure O2 (1,5 l/min) + N2/H2 (2l/min; 10 %) having, as a result, silicon gate oxides with excellent electrical characteristics. To obtain P+ polysilicon, it Spin On Glass (SOG) of boron the wafers was annealed at 950, 1000, 1050 or 1100 °C during 30 min. We have chosen a diffusion recipe of 1050 °C during 30 min to obtain volumetric concentration of boron higher than 1.10\'POT.20\' cm-³ and no boron segregation to the silicon. N+ polysilicon was also obtained using phosphorus SOG and diffusion at 1050 °C during 30 min. As a result, besides no boron segregation to Si, the interface states density was low (< 1.10\'POT.11\' eV-¹cm-²) and the breakdown field of the gate oxides increased (from 14 MV/cm to 21 MV/cm) by increasing the nitrogen doses (from 1.10\'POT.13\' to 5.10\'POT.15\' at/cm²). Although a larger dispersion and increasing of the flat-band voltage have occurred as the nitrogen dose was increased, values of 1.10\'POT.15\' and 5.10\'POT.15\' at.cm-² induced flat band voltage close to the parameter workfunction difference (\'fi\'MS) which meant effective charge density in the gate dielectrics lower than about 1.10\'POT.11\' cm-².

Progress in advanced microlithography and deposition techniques have made feasible high- k dielectric materials for MOS transistors. The continued scaling of CMOS devices is pushing the Si-SiO2 to its limit to consider high-k gate dielectrics. The demand for faster, low power, smaller, less expensive devices with good functionality and higher performance increases the demand for high-k dielectric based MOS devices. This thesis gives an in-depth study of threshold voltages of PMOS and NMOS transistors using various high-k dielectric materials like Tantalum pent oxide (Ta2O5), Hafnium oxide (HfO2), Zirconium oxide (ZrO2) and Aluminum oxide (Al2O3) gate oxides. Higher dielectric constant may lead to high oxide capacitance (Cox), which affects the threshold voltage (VT) of the device. The working potential of MOS devices can be increased by high dielectric gate oxide and work function of gate metal which may also influence the threshold voltage (VT). High dielectric materials have low gate leakage current, high breakdown voltage and are thermally stable on Silicon Substrate (Si). Different kinds of deposition techniques for different gate oxides, gate metals and stability over silicon substrates are analyzed theoretically. The impact of the properties of gate oxides such as oxide thickness, interface trap charges, doping concentration on threshold voltage were simulated, plotted and studied. This study involved comparisons of oxides-oxides, metals-metals, and metals-oxides. Gate metals and alloys with work function of less than 5eV would be suitable candidates for aluminum oxide, hafnium oxide etc. based MOSFETs.

The performance and power scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over three decades. As Si complementary metal-oxide-semiconductor (CMOS) scaling is approaching the physical and optical limits, the emerging technology involves new materials for the gate dielectrics and the channels as well as innovative structures. III-V materials have much higher electron mobility compared to Si, which can potentially provide better device performance. Hence, there have been tremendous research activities to explore the prospects of III-V materials for CMOS applications. Nevertheless, the key challenges for III-V MOSFETs with high-[kappa] oxides such as the lack of high quality, thermodynamically stable insulators that passivate the gate oxide/III-V interface still hinder the development of III-V MOS devices. The main focus of this dissertation is to develop the proper processes and structures for III-V MOS devices that result in good interface quality and high device performance. Firstly, fabrication processes and device structures of surface channel MOSFETs were investigated. The interface quality of In[subscript 0.53]Ga[subscript 0.47]As MOS devices was improved by developing the gate-last process with more than five times lower interface trap density (D[subscript it]) compared to the ones with the gate-first process. Furthermore, the optimum substrate structure was identified for inversion-type In[subscript 0.53]Ga[subscript 0.47]As MOSFETs by investigating the effects of channel doping concentration and thickness on device performance. With the proper process and channel structures, the first inversion-type enhancement-mode In[subscript 0.53]Ga[subscript 0.47]As MOSFETs with equivalent oxide thickness (EOT) of ~10 Å using atomic layer deposited (ALD) HfO₂ gate dielectric were demonstrated. The second part of the study focuses on buried channel InGaAs MOSFETs. Buried channel InGaAs MOSFETs were fabricated to improve the channel mobility using various barriers schemes such as single InP barrier with different thicknesses and InP/InAlAs double-barrier. The impacts of different high-[kappa] dielectrics were also evaluated. It has been found that the key factors enabling mobility improvement at both peak and high-field mobility in In[subscript 0.7]Ga[subscript 0.3]As quantum-well MOSFETs with InP/InAlAs barrier-layers are 1) the epitaxial InP/InAlAs double-barrier confining carriers in the quantum-well channel and 2) good InP/Al₂O₃/HfO₂ interface with small EOT. Record high channel mobility was achieved and subthreshold swing (SS) was greatly improved. Finally, InGaAs tunneling field-effect-transistors (TFETs), which are considered as the next-generation green transistors with ultra-low power consumption, were demonstrated with more than two times higher on-current while maintaining much smaller SS compared to the reported results. The improvements are believed to be due to using the In[subscript 0.7]Ga[subscript 0.3]As tunneling junction with a smaller bandgap and ALD HfO₂ gate dielectric with a smaller EOT. / text

Recently, high-κ materials have become the focus of research and been extensively utilized as the gate dielectric layer in aggressive scaled complementary metal-oxide-semiconductor (CMOS) technology. Hafnium dioxide (HfO2) is the most promising high-κ material because of its excellent chemical, thermal, mechanical and dielectric properties and also possesses good thermodynamic stability and better band offsets with silicon. Hence, HfO2 has already been used as gate dielectric in modern CMOS devices. For future technologies, it is very difficult to scale the silicon transistor gate length, so it is a necessary requirement of replacing the channel material from silicon to some high mobility material. Two-dimensional layered materials such as graphene and molybdenum disulfide (MoS2) are potential candidates to replace silicon. Due to its planar structure and atomically thin nature, they suit well with the conventional MOSFET technology and are very stable mechanically as well as chemically. HfO2 plays a vital role as a gate dielectric, not only in silicon CMOS technology but also in future nano-electronic devices such as graphene/MoS2 based devices, since high-κ media is expected to screen the charged impurities located in the vicinity of channel material, which results in enhancement of carrier mobility. So, for sustenance and enhancement of new technology, extensive study of the functional materials and its processing is required. In the present work, optimization of HfO2 thin films for gate dielectric applications in Nano-electronic devices using electron beam evaporation is discussed. HfO2 thin films have been optimized in two different thickness regimes, (i) about 35 nm physical thicknesses for back gate oxide graphene/MoS2 transistors and (ii) about 5 nm physical thickness to get Equivalent Oxide Thickness (EOT) less than 1 nm for top gate applications. Optical, chemical, compositional, structural and electrical characterizations of these films have been done using Ellipsometry, X-ray Photoelectron Spectroscopy (XPS), Rutherford Back Scattering (RBS), X-ray Diffraction (XRD), Capacitance-Voltage and Current-Voltage characterization techniques. The amount of O2 flow rate, during evaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post deposition annealing (PDA) and post metallization annealing (PMA) in forming gas ambient (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O2 flow rate shows the best properties as measured on MOS capacitors. A high density film (ρ=8.2 gram/cm3, 85% of bulk density) with high dielectric constant of κ=19 and leakage current density of J=2.0×10-6 A/cm2 at -1 MV/cm has been achieved at optimized deposition conditions. Bilayer graphene on HfO2/Si substrate has been successfully identified and also transistor has been fabricated with HfO2 (35 nm) as a back gate. High transconductance compared to other back gated devices such as SiO2/Si and Al2O3/Si and high mobility have been achieved. The performance of back gated bilayer graphene transistors on HfO2 films deposited at two O2 flow rates of 3 SCCM and 20 SCCM has been evaluated. It is found that the device on the film deposited at 3 SCCM O2 flow rate shows better properties. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices. MoS2 layers on the optimized HfO2/Si substrate have been successfully identified and transistor has been fabricated with HfO2 (32 nm) as a back gate. The device is switching at lower voltages compared to SiO2 back gated devices with high ION/IOFF ratio (>106). The effect of film thickness on optical, structural, compositional and electrical properties for top gate applications has been studied. Also the effect of gate electrode material and its processing on electrical properties of MOS capacitors have been studied. EOT of 1.2 nm with leakage current density of 1×10-4 A/cm2 at -1V has been achieved.

The continuous downscaling has enforced the device size and oxide thickness to few nanometers. After serving for several decades as an excellent gate oxide layer in complementary metal oxide semiconductor (CMOS) devices, the thickness of SiO2 layer has reached to its theoretical limits. Ultra-thin films of SiO2 can result in severe leakage currents due to direct tunneling as well as maintaining the homogeneity of the layers becomes an additional challenge. The use of a high- (HK) layer can solve these twin concerns of the semiconductor industry, which can also enhance the capacitance due to superior dielectric permittivity and reduce the leakage current by being thicker than the silicon dioxide. This thesis is concerned about the development of solution route fabricated high-k (TiO2, ZrO2 and HfO2) gate dielectrics and the investigation of high-/silicon interfaces by highly sensitive DLTS technique in MOS structures. The solution processing reduce the industrial fabrication cost and the DLTS method has the advantage to accurately measure the interface related defects parameters; such as interface trap density (Dit), capture cross-section (), activation energy (ET) and also distinguish between bulk and interface traps. In this thesis, HK films have been deposited by solution route, the material and electrical properties of the film and the HK/Si interface have been extensively evaluated. IN CHAPTER 1, we have summarized the history and evolution of transistor and it provides the background for the work presented in this thesis. IN CHAPTER 2, we have described the experimental method /technique used for the fabrication and characterization. The advantages and working principals of spin-coating and DLTS techniques are summarized. IN CHAPTER 3, we have presented the preparation and optimization of TiO2 based HK layer. Structural, surface morphology, optical electrical and dielectric properties are discussed in details. A high- 34 value is achieved for the 36 nm TiO2 films. IN CHAPTER 4, we presented the technologically relevant Si/TiO2 interface study by DLTS technique. The DLTS analysis reveals a small capture cross-section of the interface with acceptable interface state density. IN CHAPTER 5, we have focused on the fabrication of amorphous ZrO2 films on p-Si substrate. The advantage of amorphous dielectric layer is summarized as first dielectric reported SiO2 is used in its amorphous phase. The moderate-15 with low leakage current density is achieved. IN CHAPTER 6, the HfO2 films are prepared using hafnium isopropoxide and a high value of dielectric constant 23 is optimized with low leakage current density. The current conduction mechanisms are discussed in details. IN CHAPTER 7, we have probed the oxygen vacancy related sub-band-gap states in HfO2 by DLTS technique. IN CHAPTER 8, we have presented the summary of the dissertation and the prospect research directions are suggested. In summary, we have studied the group IVB transition metal elemental oxides (TMEO); TiO2, ZrO2 and HfO2 thin films in the MOS structure, as a possible replacement of SiO2 gate dielectric. For the TMEO films deposition a low-cost and simple method spin-coating was utilized. The film thicknesses are in the range of 35 – 39 nm, which was measured by ellipsometry and confirmed with the cross-sectional SEM. A rough surface of gate dielectric layer can trap the charge carrier and may cause the Fermi level pinning, which can cause the threshold voltage instabilities. Hence, surface roughness of oxide layer play an important role in CMOS device operation. We have achieved quite good flat surfaces (RMS surface roughness’s are 0.2 – 2.43 nm) for the films deposited in this work. The TiO2 based MOS gate stack shows an optimized high dielectric constant ( 34) with low leakage current density (3.710-7 A.cm-2 at 1 V). A moderate dielectric constant ( 15) with low leakage current density (4.710-9 A.cm-2 at 1 V) has been observed for the amorphous ZrO2 thin films. While, HfO2 based MOS gate stack shows reasonably high dielectric constant ( 23) with low leakage current density (1.410-8 A.cm-2 at 1 V). We have investigated the dominating current conduction mechanism and found that the current is mainly governed by space charge limited conduction (SCLC) mechanism for the high bias voltages, while low and intermediate bias voltages show the (Poole – Frenkel) PF and (Fowler – Nordheim) FN tunneling, respectively. For the HfO2 MOS device band alignment is drawn from the UPS and J-V measurements. The band gap and electron affinity of HfO2 films are estimated 5.9 eV and 3 eV, respectively, which gives a reasonable conduction band offset (1.05 eV) with respect to Si. A TMEO film suffers from a large number of intrinsic defects, which are mostly oxygen vacancies. These defects can create deep levels below the conduction band of high- dielectric material, which can act like a hole and electron traps. In addition to that, interface between Si and high- is an additional concern. These defect states in the band gap of high- or at the Si/ high- interface might lead to the threshold voltage shifts, lower carrier mobility in transistor channel, Fermi level pinning and various other reliability issues. Hence, we also studied bulk and interfacial defects present in the high- films on Si and their interface with Si by a very sensitive DLTS technique. The capture cross-sections are measured by insufficient filling DLTS (IF – DLTS). The defects present at the interface are Si dandling bond and defect in the bulk are mostly oxygen vacancies related defects present in various charge states. The interface states (Dit) are in the range of 2×1011 to 9×1011 eV-1cm-2, which are higher than the Al/SiO2/Si MOS devices (Dit in Al/SiO2/Si is the benchmark and in the order of 1010 eV-1cm-2). Still this is an acceptable value for Si/high-k (non-native oxide) MOS devices and consistent with other deposition methods. The capture cross-sections are found to be quite low in the order of 10-18 to 10-19 cm2, which indicate a minor impact on the device operation. The small value of capture cross-sections are attributed to the involvement of tunneling, to and from the bulk traps to the interface. In conclusion, the low cost solution processed high- thin films obtained are of high quality and find their importance as a potential dielectric layer. DLTS study will be helpful to reveal various interesting facts observed in high- such as resistive switching, magnetism and leakage current problems mediated by oxygen vacancy related defects