4H-SiC based Metal-Oxide Semiconductor(MOS) capacitors are promising key components for next generation power devices. For high frequency power applications, however, there is a major drawback of this type of devices, i.e. they have low inversion channel mobility that consequently affects the switching operation in MOS Field-Effect Transistors (MOSFETs). Carbon clusters or excess carbon atoms in the interface between the dielectric layer and SiC is commonly considered to be the carrier trapping and scattering centers that lower the carrier channel mobility. Based on the previous work in the research group, a new fabrication process for forming the dielectric layer with a lower density of the trap states is investigated. The process consists of standard semiconductor cleaning, pre-treatments, pre-oxidation, plasma enhanced chemical vapor deposition (PECVD) and post oxidation annealing. I-V measurements of the dielectric strength showed that the resulting layers can sustain proper working condition under an electric field of at least 5MV/cm. C-V characteristics measurements provided the evidence that the proposed method can effectively reduce the interfacial states, which are main culprit for a large flat band voltage shift of C-V characteristics, in particular under annealing at 900°C in nitrogen atmosphere.

The work deals with the capacitance measurement of high-voltage PN junctions. The work is divided into theoretical and practical parts. The theoretical part presents insight into the fundamental properties of PN junctions and methods for measuring of the capacitance of PN junctions, primarily by C-V measurement. In the practical part, several kinds of measuring circuits are introduced and a suitable method of measurement is found. The calculations of basic parameters - the width of the base and resistivity are presented and discussed. The results were compared with the values obtained by calculation from the technological parameters of the junction.