A novel large-scale silicon system platform with 9.6cm² of active silicon interposer area is demonstrated. The platform contains three interposer tiles and two silicon bridges, and a novel self-alignment technology utilizing positive self-alignment structures (PSAS) and a novel mechanically flexible interconnect (MFI) technology are developed and used to align and interconnect tiles and bridges on an FR4 substrate. An accurate alignment < 8μm between silicon bridges and interposer tiles makes it possible to accommodate nanophotonics to enable a high bandwidth and low-energy system in the future. In addition, mechanically flexible interconnects and silicon bridges are used to provide electrical connections between interposer tiles without having to use motherboard-level interconnects. Finally, an elastomeric bump interposer is developed to enable the packaging of PSAS-enabled silicon systems, and PSAS' compatibility with a thermo-compression bonding process is demonstrated to enable a wide range of system configurations involving interposer tiles and bridges, including the multi-chip package configuration used with the elastomeric bump interposers.

The advent of smart and wearable systems along with their Internet of Things (IoT) applications are driving unparalleled product miniaturization and multifunctional integration with computing, wireless communications, wireless healthcare, security, banking, entertainment, and navigation and others. This evolution is primarily enabled by the integration of multiple technologies such as RF, analog, digital, MEMS, sensors and optics in the same system. Integration of these heterogeneous technologies creates a new need for multiple power supply rails to provide device-specific voltage and current levels. Hence, multiple power converters, each requiring several passive components, are used to create stable power-supplies. However, state-of-art power supplies employ SMD passives that are relatively large, forcing these modules to be placed on the board far from the active IC. This leads to significantly sub-par frequency performance and poses a challenge for ultra-miniaturized and reliable power supplies. Hence, novel packaging technologies that can improve miniaturization, electrical performance and reliability at a relatively low-cost are required to address these challenges. Georgia Tech-PRC proposes 3D integration of passives and actives (3D IPAC) as doubleside thin components on ultra-thin glass substrates with through-package-vias (TPVs) to meet these requirements. This thesis focuses on a comprehensive methodology to demonstrate a 3D IPAC power module, starting with modeling, design, fabrication and characterization to validate 3D integrated ultra-thin inductors and capacitors in ultra-thin substrates. Another key focus of this thesis is to advance building block technologies such as thinfilm inductors and capacitors to achieve the target properties for 3D IPAC integration. As a first building block technology, advanced capacitor technologies were explored with high-k thinfilm barium strontium titanate dielectrics and lanthanum nickel oxide electrodes as an alternative to Cu, Ni and Pt electrodes for improved performance and cost. The BST capacitors with LNO electrodes resulted in a capacitance density of 20-30 nF/cm2 with leakage as low as nA/nF up to 3 V. A glass-compatible process was developed with crystallization temperatures less than 650 C. These capacitors with thinfilm electrodes and dielectrics can be integrated into ultra-thin interposers and packages. This can help improve the capacitor performance up to the GHz range. As a next build block, Si-nanowires were studied as high surface area electrodes for high-density capacitors. Analytical modeling was performed to understand the length of the nanowires based on the catalyst size. This modeling study was then extended to understand the cut-off frequency of the capacitors based on the RC time constant. The wires were fabricated using both chemical vapor deposition (CVD) and wet-etch processes. However, it was noticed that the wet-etch process provided more control on the geometry, density and orientation of the nanowires. Si-oxide was thermally grown on the surface of the wires. A capacitance density of 200 nF/mm2 was achieved. It was noticed that the cut-off frequency of such capacitors was limited to the lower kHz range. However, the operating frequency can be improved by simply using a highly conductive Si-substrate. The second part of the thesis focuses on inductor and capacitor integration on ultra-thin glass substrates for high-frequency power modules using the 3D IPAC approach. Analytical models were used to calculate the required passive component values based on the target frequency, ripple currents and voltages of the power module. Next, a SPICE model was used to optimize the value of the required passives based on the output parasitics. The L and C structures were then modeled using 2.5D method of moments (MOM) approach. The modeling results showed 7-8 X improvement in Q-factor when the structures were fabricated using the 3D IPAC approach relative to those fabricated on the same side of the substrate. A fabrication process flow was designed based on through-via and doubleside metallization with semi-additive patterning (SAP). The components were fabricated as thinfilms on either sides of the substrate and interconnected with through-vias. The LC network was characterized using a two-port vector network analyzer. The results showed low-pass filter response, which matched the design targets of cut-off frequencies upto 100 MHz. This study, therefore, demonstrates advanced thinfilm component technologies for ultra-high frequency power-supply. It also presents, for the first time, a 3D integrated passives and actives (3D IPAC) approach with integrated L and C for power modules.

Increasing bandwidth demands for cloud computing and autonomous applications push the need for system scaling instead of transistor scaling as predicted by Moore’s Law. Optoelectronic interconnections have the potential to enable system scaling at higher bandwidth, power efficiency, and lower cost than copper wiring. The objective of this research is to demonstrate polymer-based optical waveguides with integrated optical turning structures in ultra-thin glass interposers, for fiber-to-chip or chip-to-chip optical interconnections. The fundamental material and process challenges associated with achieving this objective are encompassed in: (1) polymer-glass interfaces and adhesion, (2) lithographically-defined polymer waveguides, and (3) integrated turning structures by inclined lithography. Process guidelines for substrate preparation, adhesion enhancement, and lithographic precision of siloxane-based polymer waveguides in glass were established by fundamentally breaking down and optimizing each process step. In addition, a new process was demonstrated to achieve, for the first time, waveguides with integrated turning structures with self-alignment and symmetry in a single exposure. The new process was enabled by fabricating pre-existing, direct-coated, metallic masks before the inclined exposure step. The demonstrated structures were imaged by polished cross-sectioning and Scanning Electronic Microscopy (SEM).

Effective power delivery in Double-sided 3-D glass interposer packages was proposed, investigated, and demonstrated towards achieving high logic-to-memory bandwidth. Such 3-D interposers enable a simpler alternative to direct 3-D stacking by providing low-loss, wide-I/O channels between the logic device on one side of the ultra-thin glass interposer and memory stack on the other side, eliminating the need for complex TSVs in the logic die. A simplified PDN design approach with power-ground planes was proposed to overcome resonance challenges from (a) added parasitic inductance in the lateral power delivery path from the printed wiring board (PWB), due to die placement on the bottom side of the interposer, and (b) the low-loss property of the glass substrate. Based on this approach, this dissertation developed three important suppression solutions using, (a) the 3-D interposer package configuration, (b) the selection of embedded and SMT-based decoupling capacitors, and (c) coaxial power-ground planes with TPVs. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board (PWB) and chip-level models. Two-metal and four-metal layer test vehicles were fabricated on 30-μm and 100-μm thick glass substrates using a panel-based double-side fabrication process, for potential lower cost and improved electrical performance. The PDN test structures were characterized upto 20 GHz, to demonstrate the measured verification of (a) 3-D glass interposer power delivery network and (b) resonance suppression. The data and analysis presented in this dissertation prove that the objectives of this research were met successfully, leading to the first demonstration of effective PDN design in ultra-thin (30-100μm), and 3-D double-sided glass BGA packages, by suppressing the PDN noise from mode resonances.