High bandwidth of networks demands high performance communication processors that integrate application processing, network processing, and system support functions into a single, low cost System-On-Chip (SOC) solution. However, conventional processors, when used in network related applications, are beset by the overhead of save/restore of register context, cache misses due to fetching interrupt handler from memory, and the possibility of NIC buffer overflow. Therefore, this paper analyzes the effectiveness of multithreading to service interrupts on an embedded processor from the perspective of a Network processor and a Communication processor. A Simulation environment enhanced with a multithreaded hardware execution model is used and our results reveal that multithreading for interrupts from a single NIC brings a fair improvement in performance of Network processors and little or no effect on Communication processors. However, our analysis also show that multithreading for interrupts has a lot of potential when applied to communication processors with multiple interrupt sources, such as Ethernet, ATM, USB, and HDLC. Index terms: Multithreading, UDP, IP, device driver, interrupt processing, communication processor. / Graduation date: 2003

Optical buffers are essential components of future optical switches for resolving contentions among arriving packets. Currently, optical buffers are composed of Fiber Delay Lines (FDL). Unlike the conventional electronic buffer, optical buffer only has finite time resolution, which introduces a void period between two successive buffered packets. The void period leads to service interruptions and deteriorates the buffer performance. We develop a queueing system with exceptional service for the first packet in each busy period to model the buffer behavior. For the first time, the closed-form expressions of packet blocking probability and mean delay of optical buffer are derived. We show that the packet blocking probability can be minimized by finding the optimal FDL time granularity. This optimal granularity is neither sensitive to packet length distribution, nor sensitive to the buffer length, it is mainly determined by the traffic load. / Service interruption is a special case of varying service rate. A current trend in wireless communication is to enable devices to operate using many different transmission rates. This motivates us to develop the queueing models with varying service rate. We apply the continuous time Markov chain to characterize the service rate varying process, and develop a queueing system with Markov-modulated service rate. In this kind of problem, due to the complex interaction between the rate varying process and packet arrival process, it is hard to characterize the server state evolvement; this makes it difficult to get an analytical solution, even the server only has two service rates. To escape the trap, first, we develop a discrete time Markov chain to model the server state transition process, which makes our problem to be easily manipulated. Second, apart from the previous methods, we concentrate on the moments of the packet number in system. We find the recursive relationship between the moments of packet number, this fundamental relationship widely exists in the birth-death queue systems. Our results provide a new methodology to the design of communication systems with varying service rate. / This thesis is aimed to study the interaction between service interruption and the operation of communication systems, and develop analytical methods to help the design and optimization of communication systems with interrupted services. Our work are focused on two systems: optical buffer and wireless sensor network. The common ground of these two problems is they both present the features of service interruption. / Wireless sensor network is an ad hoc network consisting of hundreds of sensor nodes equipped with limited power sources, transmission range and functionality. A simple and effective way to save energy and prolong the network lifetime is to let the nodes interrupt their sensing and data transmission process, enter sleep mode randomly. However, sleep mode corresponds to low power consumption as well as to reduced network capacity, increased latency and slowed system response. We develop a queueing model with server shutting down in a varying neighborhood to model the behavior of sensor nodes, Combining the node queueing model and the network flow balance model, we construct an analytical framework to model the network performance, derive the network capacity, packet delivery delay and node responsive property. We also develop a node power consumption model, which takes the node sleep to active transition frequency into consideration. Our results demonstrate that the sleep/active dynamics produces the predominant impact on the average power consumption and packet delay, and properly choosing the time scale of sleep/active cycle is vital to design a power-efficient sensor network. / Liu Jianming. / "Apr. 2006." / Adviser: Tony Tong Lee. / Source: Dissertation Abstracts International, Volume: 67-11, Section: B, page: 6623. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (p. 109-117). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

<p>This thesis is about a number of improvements and additions done to a soft CPU optimized for field programmable gate arrays (FPGAs). The goal has been to implement the changes without substantially lowering the CPU's ability to operate at high clock frequencies. The result of the thesis is a number of high clock frequency modules, which when added completes the CPU hardware functionality in certain areas. The maximum frequency of the CPU is however somewhat lowered after the modules have been added.</p> / <p>Detta examensarbete handlar om ett antal förbättringar och utökningar av en mjuk processor speciellt anpassad för fältprogrammerbara grindmatriser (FPGA). Målet har varit att göra förändringarna utan att göra större avkall på processorns förmåga att operera i höga klockfrekvenser. Resultatet av examensarbetet är ett antal moduler som klarar av höga frekvenser och kompletterar processorns hårdvarufunktioner. Dock reduceras maxfrekvensen på processorn något med modulerna tillagda.</p>

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This thesis is about a number of improvements and additions done to a soft CPU optimized for field programmable gate arrays (FPGAs). The goal has been to implement the changes without substantially lowering the CPU's ability to operate at high clock frequencies. The result of the thesis is a number of high clock frequency modules, which when added completes the CPU hardware functionality in certain areas. The maximum frequency of the CPU is however somewhat lowered after the modules have been added. / Detta examensarbete handlar om ett antal förbättringar och utökningar av en mjuk processor speciellt anpassad för fältprogrammerbara grindmatriser (FPGA). Målet har varit att göra förändringarna utan att göra större avkall på processorns förmåga att operera i höga klockfrekvenser. Resultatet av examensarbetet är ett antal moduler som klarar av höga frekvenser och kompletterar processorns hårdvarufunktioner. Dock reduceras maxfrekvensen på processorn något med modulerna tillagda.

This diploma thesis deals with designing and manipulating a robot for training table tennis. Robot's mechanical construction is based on aluminium profiles supported by various standardized assembly units, such as rotating bearings, plain bearings, threaded rods... The front-end part of the robot, which requires better deformation property and lighter weight, was made from ABS material using 3D rapid prototyping technology. The design of the robot allows its body to rotate around three axises. Thanks to the high dynamical ability, robot can be set to throw balls to various places on the playing table, with different types of ball spin. Balls will be shot out by two rubber wheels, which are attached to two electrical DC motors. By driving the speed of the two motors, we can control the speed of the ball, as well as speed of its spin. All robot's activities are driven by an embedded system designed using microcontroller ATMega128. A firmware for controlling robot's function was writen and flashed into the microcontroller. End-users might communicate with the robot via a system of buttons and a text LCD display. The built robot was tested and it has shown its ability to throw balls to 6 different places of the playing table, at different speeds, with different types of ball spin, and different spin speed, according to the parameters set by user.