Thin film solar cells with Copper Indium Gallium Diselenide (Cu(In,Ga)Se2) absorber layers is one of the most promising candidates to emerge as an efficient solar cell technology in the near future. CIGS cells with efficiencies of 19.2 % have already been reported [1]. In this study, CIGS absorber layers are fabricated by a two-stage all-solid-state manufacture-friendly process. In the first stage, designated as precursor deposition, Copper and Gallium are sequentially deposited followed by co-deposition of Indium and Selenium. In the second stage, designated as selenization, the substrate is annealed at high temperatures in a selenium environment during which a thin layer of copper is also deposited. The typical thickness of the absorber layers fabricated by this process is around 2um. The ZnO transparent front contact of these cells is a bi-layer with a thin intrinsic layer and a thicker Al doped n-type layer. These layers have been fabricated by different methods using Al-doped and undoped ZnO targets. The effect of the intrinsic layer thickness on the device performance was studied. Best performances were obtained when the intrinsic layer was around 350° thick and fabricated from an Al-doped ZnO target with excess oxygen partial pressure during deposition. The main focus of this work is to reduce the thickness of the CIGS absorber layers with no or minor loss in efficiency as this would translate directly into reduction in production costs and the amount of material being used. Reducing the thickness can be done either by reducing the deposition rates or duration of deposition. Due to the complex time-temperature profile during fabrication, reducing the thickness by reducing the deposition time would also affect the duration for which the substrates will be at high temperatures. To understand what effect this would have in film formation and performance of the device, and if any post-deposition annealing would be required to compensate for the reduced time at temperatures, experiments were carried out with the cells being annealed at different stages before and after completion of the device itself. Annealing was done at 250°C in both air and vacuum. Although annealing the finished devices always yielded poorer performance, it was certainly helpful in understanding which aspects of the device were affected. Devices with reduced absorber layer thicknesses of 1.5um, 1.0um and 0.65um were fabricated. The devices showed improved Voc's when the absorber layer thickness was reduced to 1.5um and 1.0um but the Jsc's dropped by 2-3 mA/cm2. The 1.0um thick devices also showed an increase in band gap. The thickness of the Molybdenum back contact layer was increased to see if the amount of Sodium from the substrate had any effect on the device performance. The Ga/In ratio was altered and its effect was also studied. The 0.65um thick devices showed a large reduction in Voc's and Jsc's. The effect of Selenization time and Selenium flux during Selenization were studied at each of the different thicknesses.