A novel CMOS inverter has been proposed. We utilize gated N-I-P transistor to replace the conventional PMOSFET for solving the problem of width compensation. Also, we carefully investigate and analyze the non-conventional CMOS characteristics with NTFET and/or UTB JL MOSFET as driver and gated N-I-P transistor as a load. According to the results, our proposed novel CMOS inverter has correct logic behavior and its delay time is reduced about 87.2 % when compared with the CTFET. Also, our proposed CMOS still can get a 43.2 % reduction in delay time when compared with JL CMOS. In addition, because of the N-type output drain node and the SOI structure, our proposed CMOS does not need any physical isolation technique, thereby improving the packing density. Our proposed CMOS indeed obtain a 54.1 % reduction of the total area compared with the conventional CMOS. Our proposed CMOS also can achieve a 40.1 % reduction in the total area when compared with the SOI-based CMOS. More importantly, due to the reduced process steps, the cost reduction can be achieved. We therefore believe that a high packing density novel CMOS inverter with reduced process steps can become one of the contenders for future CMOS scaling.