<p>This thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.</p>

This thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.

Eddy current (EC) based testing and measurement methods are well known in non-destructive testing (NDT) world. EC sensors are extensively studied and used for material health monitoring and its property measurement. Target displacement measurement is one of the well-known applications of EC method. The main advantage of EC sensor is its working capability in harsh environment like humidity, contamination etc. It is non-contact, rugged and requires less maintenance. The range and sensitivity of target displacement is mainly determined by the probe geometry and its construction method. Also displacement measurement depends upon geometry and electromagnetic (EM) properties of the target plate. Any variation of ambient temperature alters the EM properties of the probe as well as EM properties of the target. Thus, many parameters like geometry, EM properties and temperature involved in target displacement measurement. Hence, while using EC sensor for displacement measurement, it demands careful design and measurement procedure to achieve high sensitivity and high precision with low temperature drift. To achieve these, we present the following. 1) A temperature compensation technique 2) Optimization of probe geometry and its construction method to increase the range and sensitivity 3) Selection of suitable probe measurement parameter (Z, R, X) based on target material properties 4) Making the displacement measurement less sensitive to tolerance in probe construction parameter. A temperature compensation technique for target displacement measurement, using a self-running LC oscillator has been presented. A sensing coil is energized by a Hartley oscillator. The oscillator voltage is maintained at a constant level by a closed loop feedback circuit and the average feedback current to the oscillator is measured for target displacement detection. The temperature drift of the feedback current is compensated by applying temperature compensation function (TCF) and this is verified experimentally. Cold rolled mild steel (carbon steel) is taken as a target material and the sensor is tested over a temperature range of 20 °C – 80 °C. It shows that the temperature drift is less than ±30 ppm/°C over 3 mm target displacement. To match all the sensor modules in mass production, components selection procedure is presented. To avoid mismatch across sensors in manufacturing process, the transistor based oscillator is modified with operational trans-conductance amplifier (OTA). The same temperature compensation formula (TCF) is applied to compensate the temperature drift of feedback current and achieved intended accuracy. Geometry and construction parameters of the eddy current sensing probe is optimized for target displacement measurement using Ansoft Maxwell, electromagnetic design software. EC probe with different geometry are analyzed in search of suitable geometry for target displacement measurement. Four shapes of commercially available core have been chosen for probe construction. For each shape of sensing probe, the radius and height of the probe is increased by 0 mm to 9 mm to find the effect of them on sensitivity and range of target displacement measurement. It has been observed that the probe with less height and maximum diameter has shown better performance. In addition to that, the probe geometry is optimized to achieve more sensitivity and range within the space available for probe mounting. It helps to utilize the available space effectively for probe design. Coil winding and mount-ing it inside the core window also important parameter in probe design. It has been observed that de-pressing the sensing coil inside the core window from sensing face by 3 mm decreases the sensitivity by 40 %. Hence, it is recommended to place the coil on the extreme end of the sensing face of the core. To know the effect of core permeability, it is varied from 1000 to 15000. It has been observed that it has no effect on sensitivity and measurement range. Only optimizing the probe geometry and its construction method is not adequate for target displacement measurement. We know that the EC based displacement measurement is also target material dependent. Generally probe impedance is measured and then the temperature drift of the sensing coil resistance is compensated to know the target displacement. Most of the temperature compensation techniques use this compensation technique and it is shown that those are suitable for high conductivity targets like copper. Choosing Z for displacement measurement may not be only best choice for all target materials. The displacement can be measured also through either R or X of the probe. Choosing the proper probe parameter for a given target material will provide a less temperature drift for target displacement measurement. To know about this, a simulation has been made for target displacement measurement with target metal of μr = 1, relative permittivity εr =1, and temperature coefficient of resistivity ∝ = 0.004 K-1. The conductivity (σ) of the target is varied from 1×106 S/m to 62×106 S/m in the temperature range of 20 ℃ – 80 ℃. Now the simulation has been repeated by fixing  as a constant and varying target μr. The metal plate with  = 1×106 S/m, εr=1 and ∝ = 0.004 K – 1 is taken as a target and μr is varied from 100 to 10000. For both conductivity and permeability sweep analysis, the target displacement is measured as a function of Z, R and X independently. The temperature drift in displacement measurement is also analysed for the above temperature range. An experiment has been conducted with copper, stainless steel and mild steel as target metal in the temperature range of 20 ℃ – 80 ℃. The temperature drift is calculated when the displacement is measured as function of Z, R and X. Based on the results, we have identified that the target material relative permeability determines the selection of probe measurement parameter for target displacement measurement. Hence, knowing tar-get r alone suffice to select the probe measurement parameter (Z or R or X) for displacement measurement. Optimizing the probe geometry, selecting the proper probe measurement parameter and temperature compensation technique suffice to provide a good sensitivity, range and low temperature drift for a single probe. But in general, one of the mass produced probes is selected as a reference probe and it is calibrated against the ambient temperature and target displacement. And the calibration curves are loaded to all the probes. Matching the probe construction parameters to each other across the production patches is not possible in mass production. This makes the temperature compensation function and displacement calibration are different for every individual probes for displacement measurement. This degrades the measurement accuracy. A simulation has been performed with pot core with commercial tolerance. Using this, we have obtained 24 probes due to variations in 1) Individual and few combinational variations in core and coil dimensions 2) Core permeability variation and 3) relative position of the coil with respect to core. Finally, we have quantified the displacement error for each probe. We have identified the important probe dimensional parameters that have to be controlled precisely in mass production to improve the measurement accuracy. It shows error of 0.86 % in the displacement measurement when the relative reactance and relative displacement is used for measurement. In practice, error in displacement measurement due to both the ambient temperature drift and the tolerance in probe construction parameter exist simultaneously. Hence, the combined error is computed for the target displacement range of 0 mm – 3 mm for the temperature range of 0 °C – 100 °C. The total error of less than 1 % is achieved for commercial standard probe tolerance. Finally, we have provided general factory production procedure and user calibration procedure of probe design to achieve cost effective displacement measurement with sensitivity and range with low temperature drift.

Ο στόχος της διπλωματικής αυτής εργασίας είναι η μελέτη ενός διαφορικού ταλαντωτή Collpits ο οποίος λειτουργεί ως διαιρέτης συχνότητας με έγχυση ρεύματος στην πηγή, χαμηλού θορύβου και διαφορικής εισόδου, ως προς την κατανάλωση και το θόρυβο. Επίσης συγκρίνεται η απόδοσή του σε αυτούς τους τομείς με την απόδοση άλλων τοπολογιών αναλογικών διαιρετών συχνότητας αλλά και ψηφιακών. / The objective of this thesis is to study a Collpits differential oscillator which works as a low noise and differential input, current source injection frequency divider, by taking into account consumption and noise. Also the performance in these areas is compared with other topologies of analogue and/or digital frequency dividers.

Ο σχεδιασμός αναλογικών κυκλωμάτων σε υψηλές συχνότητες είναι αδιαμφισβήτητα μία από τις σημαντικότερες εφαρμογές στον τομέα των ηλεκτρονικών. Οι προκλήσεις που καλείται να αντιμετωπίσει ο σχεδιαστής είναι πολλές και σημαντικές, καθώς τα κυκλώματα μικραίνουν σε μέγεθος και είναι απαραίτητο να δημιουργηθούν νέα μοντέλα περιγραφής των στοιχείων ολοκληρωμένων κυκλωμάτων. Παράλληλα, τα παρασιτικά φαινόμενα που επεισέρχονται στον σχεδιασμό των αναλογικών κυκλωμάτων δημιουργούν πολλές φορές trade – off μεταξύ των διαφόρων σχεδιαστικών απαιτήσεων που πρέπει να ικανοποιηθούν. Στα πλαίσια της παρούσας διπλωματικής, επικεντρώνομαι στη μελέτη και στο σχεδιασμό ταλαντωτών ελέγχομενων από τάση (VCOs). Πιο συγκεκριμένα, μελετώ τα χαρακτηριστικά δύο κατηγοριών των ταλαντωτών αυτών : των ταλαντωτών L-C και των ταλαντωτών δακτυλίου (ring). Αρχικά δίνω μία γενική περιγραφή των ταλαντωτών και των μοντέλων περιγραφής τους. Στη συνέχεια αναλύω τις πηγές θορύβου στα ολοκληρωμένα κυκλώματα και δίνω έμφαση στη θεωρία θορύβου φάσης, παρουσιάζοντας μοντέλα περιγραφής του. Στη συνέχεια, παρουσιάζω τη σχεδίαση ταλαντωτών L – C και ring, δίνοντας και τα αποτελέσματα εξομοιώσεων. Τέλος, εκτός από τα συμπεράσματα που βγαίνουν μέσω των εξομοιώσεων, γίνεται και σύγκριση μεταξύ των δύο κατηγοριών ταλαντωτών. / The design of analog circuits operating at high frequencies is undoubtedly one of the most important applications in the field of electronics. The challenges that the designer needs to face are many and important, as the circuits become smaller and smaller and is imperative that new models need to be made that describe the operation of the transistors. Furthermore, the parasitics that are inherent in any analog design create a trade – off between several design specifications that need to be satisfied. In this work I emphasize on the study and design of voltage controlled oscillators (VCOs). More specifically, I study the characteristics of two major categories of such oscillators: L-C oscillators and ring oscillators. At start, I present a general description of oscillators and the models that describe their operation. Next, I analyze the various noise sources in analog integrated circuits and I emphasize on phase noise theory, by presenting its models. In the fourth and fifth chapter, I show the design of L – C and ring oscillators, while I give the results of the simulations. Finally, apart from the conclusion drawn from the simulations, I make a comparison between the two oscillators’ categories.

The radio frequency (RF) spectrum as a natural resource is severely under-utilized over time and space due to an inefficient licensing framework. As a result, in-creasing cellular and wireless network usage is placing significant demands on the licensed spectrum. This has led to the development of cognitive radios, software defined radios and mm-wave radios. Cognitive radios (CRs) enable more efficient spectrum usage over a wide range of frequencies and hence have emerged as an effective solution to handle huge network demands. They promise versatility, flex-ability and cognition which can revolutionize communications systems. However, they present greater challenges to the design of radio frequency (RF) front-ends. Instead of a narrow-band front-end optimized and tuned to the carrier frequency of interest, cognitive radios demand front-ends which are versatile, configurable, tun-able and capable of transmitting and receiving signals with different bandwidths and modulation schemes. The primary purpose of this thesis is to design a re-configurable, wide-band and low phase-noise fast settling frequency synthesizer for cognitive radio applications. Along with frequency generation, an area efficient multi-band low noise amplifier (LNA) with integrated built-in-self-test (BIST) and a strong immunity to interferers has also been proposed and implemented for these radios. This designed LNA relaxes the specification of harmonic content in the synthesizer output. Finally some preliminary work has also been done for mm-wave (V-band) frequency synthesis. The Key Contributions of this thesis are: A frequency synthesizer, based on a type-2, third-order Phase Locked Loop (PLL), covering a frequency range of 0.1-5.4 GHz, is implemented using a 0.13 µm CMOS technology. The PLL uses three voltage controlled oscillators (VCOs) to cover the whole range. It is capable of switching between any two frequencies in less than 3 µs and has phase noise values, compatible with most communication standards. The settling of the PLL in the desired state is achieved in dynamic multiple steps rather than traditional single step settling. This along with other circuit techniques like a DAC-based discriminator aided charge pump, fast acquisition pulse-clocked based PFD and timing synchro-negation is used to obtain a significantly reduced settling time A single voltage controlled LC-oscillator (LC-VCO) has been designed to cover a wide range of frequencies (2.0-4.1 GHz) using an area efficient and switch-able multi-tap inductor and a capacitor bank. The switching of the multi-tap inductor is done in the most optimal manner so as to get good phase-noise at the output. The multi-tap inductor provides a significant area advantage, and in spite of a degraded Q, provides an acceptable phase noise of -123 dBc/Hz and -113 dBc/Hz at an offset of 1 MHz at carrier frequencies of 2 and 4 GHz, respectively. Implemented in a 0.13 µm CMOS technology, the oscillator with ≈ 69 % tuning range, occupies an active area of only 0.095 mm2. An active inductor based noise-filter has been proposed to improve the phase-noise performance of the oscillator without much increase in the area. A variable gain multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (0.8 GHz to 2.4 GHz) using an area efficient switchable-π network. The LNA can be tuned to different gain and linearity combinations for different band settings. Depending upon the location of the interferers, a specific band can be selected to provide optimum gain and the best signal-to-intermodulation ratio. This is accomplished by the use of an on-chip Built-in-Self-Test (BIST) circuit. The maximum power gain of the amplifier is 19 dB with a return loss better than 10 dB for 7 mW of power consumption. The noise figure is 3.2 dB at 1 GHz and its third-order intercept point (I I P3) ranges from -15 dBm to 0 dBm. Implemented in a 0.13 µm CMOS technology, the LNA occupies an active area of about 0.29 mm2. Three different types of VCOs (stand-alone LC VCO, push-push VCO and a ring oscillator based VCO) for generating mm-wave frequencies have been implemented using 65-nm CMOS technology and their measured results have been analyzed