The focus of the present thesis is the circuit-level implementation of an excess loop delay compensation scheme which optimizes excess loop delay in Analog-to-Digital Converter(ADC) by using a programmable delay block and synchronizes the signal passing through Dynamic Element Matching block, used to mitigate mismatch effects of multi-bit Digital-to-Analog Converter(DAC). The proposed delay block has tuning range of T/10 to T/2 seconds, with a step size of T/30 seconds, where T is the time period (1.25 nanoseconds) of sampling signal (800 MHz) in high IF (200 MHz) Bandpass [sigma delta] ADC. The implementation details of the element rotation scheme used to calibrate the multi-bit DAC static error mismatch are also presented. Also presented is the design of high frequency highly linear Operational Transconductance Amplifier(OTA) targeted for continuous-time filters in a high resolution High Intermediate Frequency (200 MHz) Bandpass [sigma delta] ADC for Software Radio applications. Proposed OTA uses super source follower input stage to enhance its voltage-to-current conversion linearity. The design has been simulated using TSMC 0.18 μm CMOS process. The OTA has small signal transconductance of 0.9 mA/V, IM3 below -79 dB (for 0.3 Vpp input), Signal-to-Noise Ratio of 82 dB and power consumption of 6.8 mW, when tested in unity gain configuration.

Sigma-delta analog-to-digital converters are gaining in popularity in recent times because of their ability to trade-off resolutions in the time and voltage domains. In particular, continuous-time modulators are finding more acceptance at higher bandwidths due to the additional advantages they provide, such as better power efficiency and inherent anti-aliasing filtering, compared to their discrete-time counterparts. This thesis work presents the system level design of a continuous-time low-pass sigma-delta modulator targeting 11 bits of resolution over 100MHz signal bandwidth. The design considerations and tradeoffs involved at the system level are presented. The individual building blocks in the modulators are modeled with non-idealities and specifications for the various blocks are obtained in detail. Simulation results obtained from behavioral models of the system in MATLAB and Cadence environment show that a signal-to-noise-and-distortion-ratio (SNDR) of 69.6dB is achieved. A loop filter composed of passive LC sections is utilized in place of integrators or resonators used in traditional modulator implementations. Gain in the forward signal path is realized using active circuits based on simple transconductance stages. A novel method to compensate for excess delay in the loop without using an extra summing amplifier is proposed.

Sigma-delta analog-to-digital converters are gaining in popularity in recent times because of their ability to trade-off resolutions in the time and voltage domains. In particular, continuous-time modulators are finding more acceptance at higher bandwidths due to the additional advantages they provide, such as better power efficiency and inherent anti-aliasing filtering, compared to their discrete-time counterparts. This thesis work presents the system level design of a continuous-time low-pass sigma-delta modulator targeting 11 bits of resolution over 100MHz signal bandwidth. The design considerations and tradeoffs involved at the system level are presented. The individual building blocks in the modulators are modeled with non-idealities and specifications for the various blocks are obtained in detail. Simulation results obtained from behavioral models of the system in MATLAB and Cadence environment show that a signal-to-noise-and-distortion-ratio (SNDR) of 69.6dB is achieved. A loop filter composed of passive LC sections is utilized in place of integrators or resonators used in traditional modulator implementations. Gain in the forward signal path is realized using active circuits based on simple transconductance stages. A novel method to compensate for excess delay in the loop without using an extra summing amplifier is proposed.