The aim of this master’s thesis is to implement an ADC (Analog-to-Digital Converter) foraudio applications using external components together with an FPGA (Field-ProgrammableGate Array). The focus is on making the ADC low-cost and it is desirable to achieve 16-bitresolution at 48 KS/s. Since large FPGA’s have numerous I/O-pins, there are usually someunused pins and logic available in the FPGA that can be used for other purposes. This istaken advantage of, to make the ADC as low-cost as possible.This thesis presents two solutions: (1) a - (Sigma-Delta) converter with a first order passive loop-filter and (2) a - converter with a second order active loop-filter. The solutionshave been designed on a PCB (Printed Curcuit Board) with a Xilinx Spartan-6 FPGA. Bothsolutions take advantage of the LVDS (Low-Voltage-Differential-Signaling) input buffers inthe FPGA.(1) achieves a peak SNDR (Signal-to-noise-and-distortion-ratio) of 62.3 dB (ENOB (Effectivenumber of bits) 10.06 bits) and (2) achieves a peak SNDR of 80.3 dB (ENOB 13.04). (1) isvery low-cost ($0.06) but is not suitable for high-precision audio applications. (2) costs $0.53for mono audio and $0.71 for stereo audio and is comparable with the solution used today:an external ADC (PCM1807).

<p>Active safety systems for automobiles in the form of camera systems have evolved rapidly the last ten years, Autoliv Electronics in Linköping develops multiple such systems. In their development process there is a need for a Break out Box (BoB) to record and playback video and CAN data as if the camera system was used in an actual automobile. The aim of this thesis has been to develop a BoB for these camera systems. The work has been divided into three phases; identification of requirements, design of the BoB and implementation of a prototype. The project has addressed four known issues with the currently used BoB; bandwidth, modularity, synchronization and usability. The result is a new BoB which is based on an FPGA connecting to a PC over Gigabit Ethernet. The design is an extendible platform for multiple channels of video, CAN data, other serial data and future extensions. A prototype proves the design concept by successfully recording video for the Autoliv NightVision system onto a PC.</p>

Active safety systems for automobiles in the form of camera systems have evolved rapidly the last ten years, Autoliv Electronics in Linköping develops multiple such systems. In their development process there is a need for a Break out Box (BoB) to record and playback video and CAN data as if the camera system was used in an actual automobile. The aim of this thesis has been to develop a BoB for these camera systems. The work has been divided into three phases; identification of requirements, design of the BoB and implementation of a prototype. The project has addressed four known issues with the currently used BoB; bandwidth, modularity, synchronization and usability. The result is a new BoB which is based on an FPGA connecting to a PC over Gigabit Ethernet. The design is an extendible platform for multiple channels of video, CAN data, other serial data and future extensions. A prototype proves the design concept by successfully recording video for the Autoliv NightVision system onto a PC.

Submitted by Lucelia Lucena (lucelia.lucena@ufpe.br) on 2015-03-09T19:23:33Z No. of bitstreams: 2 DISSERTAÇÃO LucasTorquato de Melo.pdf: 2719347 bytes, checksum: 8fbd700a7bf5e2bb51b478109dcbd32e (MD5) license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) / Made available in DSpace on 2015-03-09T19:23:33Z (GMT). No. of bitstreams: 2 DISSERTAÇÃO LucasTorquato de Melo.pdf: 2719347 bytes, checksum: 8fbd700a7bf5e2bb51b478109dcbd32e (MD5) license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) Previous issue date: 2014 / A busca por aumento de desempenho de sistemas computacionais é cada vez maior em empresas e pesquisas científicas. Essa necessidade existe por conta do surgimento de aplicações complexas que necessitam de um grande poder computacional para serem executadas eficientemente. A utilização de arquiteturas alternativas como FPGAs nesse contexto têm sido realizada com o intuito de prover excelente desempenho na execução dessas aplicações. Atualmente, sistemas envolvendo múltiplos FPGAs são utilizados em diversas aplicações científicas. A tendência é que em tais sistemas sejam desenvolvidos de forma a permitir escalabilidade de dispositivos, possibilitando que mais FPGAs possam fazer parte da arquitetura e aumentando o desempenho. Para que esses sistemas possam funcionar de forma eficiente, utilizando paralelamente recursos existentes nos FPGAs, uma comunicação eficiente deve existir entre os FPGAs disponíveis na plataforma. Geralmente esse tipo de comunicação, em FPGAs de última geração, se dá por meio de interfaces tipo LVDS (Sinalização Diferencial de Baixa Tensão) e por meio de transceptores e receptores. A sinalização LVDS permite o envio de sinais em alta velocidade através de um par diferencial de fios paralelos. A utilização desse recurso permite que a transmissão de dados entre os dispositivos possa ser realizada de forma mais eficiente, possibilitando uma comunicação mais segura contra interferências eletromagnéticas. Outro fator importante é que o roteamento que interconecta os pinos LVDS na plataforma deve ser desenvolvido com precisão para evitar instabilidades na comunicação. Infelizmente, muitas plataformas disponíveis no mercado não observam tais restrições, limitando a taxa de transferência no barramento. Este trabalho apresenta um canal de comunicação inter-FPGAs baseado em uma interface DDR voltado para esse tipo de plataforma. Esta abordagem promove uma comunicação estável entre esses dispositivos sem a utilização de pinos LVDS. Um módulo de detecção de erro também foi desenvolvido para garantir a integridade das transferências e corrigir possíveis erros no barramento. O canal foi validado em uma plataforma comercial. Os resultados de síntese e desempenho são apresentados nesse trabalho bem como os estudos de caso envolvidos.

My thesis deals with project of LVDS busbar with high resistivity with regard to disturbance from surroundings and radiation undesirable electromagnetic waves into its environment. Project of LVDS busbar was elaborated by numeric methods and it was suggested optimal solution of the shape and material of multiply technology DPS. The project was realized on desired driving-point impenance of busbar Z=100 ohm with frequency f1=100 MHz of the first harmonic component rectangular signal of defind modality, entering and diagonal edge.

This diploma thesis deals with implementation of fast serial bus and SATA controler in the FPGA chip. The work is divided into two parts. In the first part the circuit for communication between the FPGAs is designed and in the second part the circuit for direct connection of SATA hard disk to a gate array is created. The circuit for communication between the FPGA is designed according to SATA specification. Link layer and physical layers are implemented in VHDL with programmable logic resources.

La recherche en imagerie moléculaire repose beaucoup sur les performances en tomographie d'émission par positrons (TEP). Les avancées technologiques en électronique ont permis d'améliorer la qualité de l'image fournie par les scanners TEP et d'en augmenter le champ d'application. Le scanner LabPET II, en développement à l'Université de Sherbrooke, permettra d'atteindre des résolutions spatiales inégalées.La conception de ce scanner requiert une très grande densité de détecteurs de l'ordre de 39 000 sur un anneau de 15 cm de diamètre par 12 cm de longueur axiale. D'autre part, l'Université de Sherbrooke mène également des travaux en tomodensitométrie (TDM) par comptage de photons individuels. Ces travaux s'insèrent dans un programme de recherche menant à réduire par un facteur 1,5 à 10 la dose de rayon X par rapport aux doses actuelles en TDM. Un circuit intégré (ASIC) a été développé pour supporter les performances attendues en TEP et en TDM. Cependant, la très grande densité de canaux rend inadéquate la vérification externe, sur circuits imprimés (PCB), des fonctionnalités des 64 canaux d'acquisition du circuit intégré actuellement en conception. Ainsi, un générateur de charge électronique a été conçu et intégré dans l'ASIC afin de pouvoir vérifier directement sur le circuit intégré ( On-Chip ) le fonctionnement de la chaine d'acquisition. Il permettra aussi de faire les tests pour le calcul de la résolution d'énergie et de la résolution en temps intrinsèque. La communication des données avec l'ASIC se fait par une ligne différentielle afin de maximiser l'immunité des signaux contre le bruit et d'assurer la vitesse de communication voulue.La norme Low-Voltage Differential Signaling (LVDS) a été choisie pour ce type de communication. En effet, trois récepteurs LVDS, basse consommation, ont été conçus et intégrés dans l'ASIC afin de recevoir les commandes de fonctionnement de l'ASIC à partir d'une matrice de portes programmables Field-Programmable Gate Array (FPGA) et de communiquer le signal d'horloge aux différents blocs. Pour augmenter la fiabilité du traitement effectué par l'électronique frontale, une mesure en température de l'ASIC est nécessaire. Un capteur de température basé sur la boucle à délais Delay-Locked Loop (DLL) a été conçu et intégré. En effet, la mesure de la température de l'ASIC permet d'intervenir en réalisant une compensation sur les mesures et en contrôlant le système de refroidissement en cas de sur-échauffement.

Our society increasingly relies on the transmission and reception of vast amounts of data using serial connections featuring ever-increasing bit rates. In imaging systems, for example, the frame rate achievable is often limited by the serial link between camera and host even when modern serial buses with the highest bit rates are used. This thesis documents a scalable embedded transceiver system with a bandwidth and interface standard that can be adapted to suit a particular application. This new approach for a real-time scalable embedded transceiver system is referred to as a Novel Reference Model (NRM), which connects two or more applications through a transceiver network in order to provide real-time data to a host system. Different transceiver interfaces for which the NRM model has been tested include: LVDS, GIGE, PMA-direct, Rapid-IO and XAUI, one support a specific range for transceiver speed that suites a special type for transceiver physical medium. The scalable serial link approach has been extended with loss-less data compression with the aim of further increasing dataflow at a given bit rate. Two lossless compression methods were implemented, based on Huffman coding and a novel method called Reduced Lossless Compression Method (RLCM). Both methods are integrated into the scalable transceivers providing a comprehensive solution for optimal data transmission over a variety of different interfaces. The NRM is implemented on a field programmable gate array (FPGA) using a system architecture that consists of three layers: application, transport and physical. A Terasic DE4 board was used as the main platform for implementing and testing the embedded system, while Quartus-II software and tools were used to design and debug the embedded hardware systems.

There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filter’s total harmonic distortion is less than –44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second.

There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filter’s total harmonic distortion is less than –44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second.