With VLSI(very large scale integration) technology shrinking and frequency increasing, the minimum feature size is smaller than sub-wavelength lithography wavelength, and the manufacturing cost is significantly increasing in order to achieve a good yield. Consequently design companies need to further lower power consumption. All these factors bring new challenges; simulation and modeling need to handle more design constraints, and need to work with modern manufacturing processes. In this dissertation, algorithms and new methodology are presented for these problems: (1) fast and accurate capacitance extraction, (2) capacitance extraction considering lithography effect, (3) BEOL(back end of line) impact on SRAM(static random access memory) performance and yield, and (4) new physical synthesis optimization flow is used to shed area and reduce the power consumption. Interconnect parasitic extraction plays an important role in simulation, verification, optimization. A fast and accurate parasitic extraction algorithm is always important for a current design automation tool. In this dissertation, we propose a new algorithm named HybCap to efficiently handle multiple planar, conformal or embedded dielectric media. From experimental results, the new method is significantly faster than the previous one, 77X speedup, and has a 99% memory savings compared with FastCap and 2X speedup, and has an 80% memory savings compared with PHiCap for complex dielectric media. In order to consider lithography effect in the existing LPE(Layout Parasitic Extraction) flow, a modified LPE flow and fast algorithms for interconnect parasitic extraction are proposed in this dissertation. Our methodology is efficient, compatible with the existing design flow and has high accuracy. With the new enhanced parasitic extraction flow, simulation of BEOL effect on SRAM performance becomes possible. A SRAM simulation model with internal cell interconnect RC parasitics is proposed in order to study the BEOL lithography impact. The impact of BEOL variations on memory designs are systematically evaluated in this dissertation. The results show the power estimation with our SRAM model is more accurate. Finally, a new optimization flow to shed area blow in the design synthesis flow is proposed, which is one level beyond simulation and modeling to directly optimize design, but is also built upon accurate simulations and modeling. Two simple, yet efficient, buffering and gate sizing techniques are presented. On 20 industrial designs in 45nm and 65nm, our new work achieves 12.5% logic area growth reduction, 5.8% total area reduction, 10% wirelength reduction and 770 ps worst slack improvement on average.

Abstract In this thesis, we propose a new geometrical structure of waveguide for the application of traveling-wave electroabsorption modulator (TWEAM). As approaching to high-speed performance in TWEAM, low parasitic capacitance in the waveguide is necessary to get good microwave propagation properties. In this work, a novel processing called two-step undercut-etching the active region (UEAR) is developed to reduce the parasitic capacitance. First of all, Beam Propagation Method (BPM) is used to calculate this 2-D structure optical modes ensuring the guiding capability in such kind of waveguides. Based on an equivalent circuit model, the microwave propagation on different structures of waveguide is then investigated to decide the UEAR waveguide structure. By the selectively etching solution on InP/InGaAsP, the processing by two-step UEAR is developed to reduce the parasitic capacitance in the waveguide core. H3PO4:HCl is used to selectively etch P-InP layer on the top of InGaAsP M.Q.W. (multiple quantum wells, active region). H3PO4:H2O2:H2O is subsequently and selectively remove InGaAsP M.Q.W.s to define the waveguide core. This processing has been successfully developed. The electrical transmission measurement on this kind of TWEAM shows low reflection S11 of < -17.5dB and a low insertion loss S21 of < ¡V2.7dB from D.C. to 40GHz, indicating high microwave performance on such two-step UEAR waveguide can be achieved due to the low parasitic capacitance.

Fast and accurate solvers for capacitance extraction are needed by the VLSI industry in order to achieve good design quality in feasible time. With the development of technology, this demand is increasing dramatically. Three-dimensional capacitance extraction algorithms are desired due to their high accuracy. However, the present 3D algorithms are slow and thus their application is limited. In this dissertation, we present several novel techniques to significantly speed up capacitance extraction algorithms based on boundary element methods (BEM) and to compute the capacitance extraction in the presence of floating dummy conductors. We propose the PHiCap algorithm, which is based on a hierarchical refinement algorithm and the wavelet transform. Unlike traditional algorithms which result in dense linear systems, PHiCap converts the coefficient matrix in capacitance extraction problems to a sparse linear system. PHiCap solves the sparse linear system iteratively, with much faster convergence, using an efficient preconditioning technique. We also propose a variant of PHiCap in which the capacitances are solved for directly from a very small linear system. This small system is derived from the original large linear system by reordering the wavelet basis functions and computing an approximate LU factorization. We named the algorithm RedCap. To our knowledge, RedCap is the first capacitance extraction algorithm based on BEM that uses a direct method to solve a reduced linear system. In the presence of floating dummy conductors, the equivalent capacitances among regular conductors are required. For floating dummy conductors, the potential is unknown and the total charge is zero. We embed these requirements into the extraction linear system. Thus, the equivalent capacitance matrix is solved directly. The number of system solves needed is equal to the number of regular conductors. Based on a sensitivity analysis, we propose the selective coefficient enhancement method for increasing the accuracy of selected coupling or self-capacitances with only a small increase in the overall computation time. This method is desirable for applications, such as crosstalk and signal integrity analysis, where the coupling capacitances between some conductors needs high accuracy. We also propose the variable order multipole method which enhances the overall accuracy without raising the overall multipole expansion order. Finally, we apply the multigrid method to capacitance extraction to solve the linear system faster. We present experimental results to show that the techniques are significantly more efficient in comparison to existing techniques.

As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integration (VLSI) design. In this dissertation, we study several deep submicron problems (eg. coupling capacitance, antenna effect and delay variation) and propose optimization techniques to mitigate these DSM effects in the place-and-route stage of VLSI physical design. The place-and-route stage of physical design can be further divided into several steps: (1) Placement, (2) Global routing, (3) Layer assignment, (4) Track assignment, and (5) Detailed routing. Among them, layer/track assignment assigns major trunks of wire segments to specific layers/tracks in order to guide the underlying detailed router. In this dissertation, we have proposed techniques to handle coupling capacitance at the layer/track assignment stage, antenna effect at the layer assignment, and delay variation at the ECO (Engineering Change Order) placement stage, respectively. More specifically, at layer assignment, we have proposed an improved probabilistic model to quickly estimate the amount of coupling capacitance for timing optimization. Antenna effects are also handled at layer assignment through a linear-time tree partitioning algorithm. At the track assignment stage, timing is further optimized using a graph based technique. In addition, we have proposed a novel gate splitting methodology to reduce delay variation in the ECO placement considering spatial correlations. Experimental results on benchmark circuits showed the effectiveness of our approaches.

Optical communications is expanding into new applications such as infrared wireless communications; therefore, designing high performance circuits has gained considerable importance. In this dissertation a wide dynamic-range variable-gain transimpedance amplifier (TIA) is introduced. It adopts a regulated cascode (RGC) amplifier and an operational transconductance amplifier (OTA) as the feed forward gain element to control gain and improve the overload of the optical receiver. A fully-differential variable-gain TIA in a 0.35µm CMOS technology is realized. It provides a bit error rate (BER) less than 10-12 for an input current from 6µA-3mA at 3.3V power supply. For the transimpedance gain variation, from 0.1kΩ to 3kΩ, -3dB bandwidth is higher than 1.7GHz for a 0.6pF photodiode capacitance. The power dissipations for the highest and the lowest gains are 8.2mW and 24.9mW respectively. A new technique for designing uniform multistage amplifiers (MA) for high frequency applications is introduced. The proposed method uses the multi-peak bandwidth enhancement technique while it employs identical, simple and inductorless stages. It has several advantages, such as tunability of bandwidth and decreased sensitivity of amplifier stages, to process variations. While all stages of the proposed MA topology are identical, the gain-bandwidth product can be extended several times. Two six-stage amplifiers in a TSMC 0.35µm CMOS process were designed using the proposed topology. Measurements show that the gain can be varied for the first one between 16dB and 44dB within the 0.7-3.2GHz bandwidth and for the second one between 13dB and 44dB within a 1.9-3.7GHz bandwidth with less than 5.2nV/√Hz noise. Although the second amplifier has a higher gain bandwidth product, it consumes more power and occupies a wider area. A technique for capacitance multiplication is utilized to design a tunable loop filter. Current and voltage mode techniques are combined to increase the multiplication factor (M). At a high input dynamic range, M is adjustable and the capacitance multiplier performs linearly at high frequencies. Drain-source voltages of paired transistors are equalized to improve matching in the current mirrors. Measurement of a prototype loop filter IC in a 0.5µm CMOS technology shows 50µA current consumption for M=50. Where 80pF capacitance is employed, the capacitance multiplier realizes an effective capacitance varying from 1.22nF up to 8.5nF.

The passive devices used in the wireless communication system ¡]including resistor, capacitor and inductor¡^usually need high quality factor and low power dissipation characteristics. This thesis aims to develop a micro tunable capacitor with high-quality-factor and wide-tuning-range using surface micromachining. In contrast with conventional low-tuning-rate parallel-plate tunable capacitors, this research presents a concave structure and eight-suspending-beams layout design of the top electrode to enhance the elastic rigidity and tuning rate. In addition, this study appropriately decreases the thickness of top electrode, the tuning rate of such device can be improved to 65~2100%. On the other hand, in order to substantially increase quality factor, this thesis adopted the glass substrate ¡]Corning 7740¡^to reduce the power dissipation of high frequency operating signal. The optimized quality factor of this work is approximately equal to 41 under 2.4 GHz operation frequency. The material of sacrificial layer and top electrode adopted in this dissertation is aluminum and gold respectively. To avoid any breakage of the vertical supporting beams during releasing process, this research appropriately increases the width of vertical supporting beams, however, keep the thickness of the suspending part of top electrode for the maintenance of high quality factor and low driving voltage.

Photovoltaic (PV) conversion of solar energy appears to be one of the most promising ways of meeting the increasing energy demand. In space, photovoltaic power source is the only safe alternative. Conventional silicon solar cell technologies have seen several improvements and off late GaAs/Ge and multijunction solar cells are developed to improve conversion efficiency. Demand for higher power, smaller size, lesser weight and higher efficiency has necessitated the use of high frequency switching power conditioners, which requires a better understanding of the AC characteristics of the solar cell, especially its capacitance. Solar cell is large p-n junction diode, whose AC parameters (capacitance and resistance) varies nonlinearly with its operating voltage, temperature and depend on the method (frequency or time domain) of measurement.Hence, studies on AC parameters of solar cells is taken up involving development of instrumentation, measurements on various types of solar cells and applications of AC parameters on switching shunt regulators. In the present research work a measurement set-up to measure the solar cell AC parameters using impedance spectroscopy technique is established first with the commercial instruments. Here a small AC voltage (<VT) is applied about the operating voltage (DC bias) and its complex impedance is measured from the resultant current over a wide range of frequencies. Cell capacitance, parallel resistance, series resistance and inductance are estimated from the impedance spectrum, which is plot of the cell impedance in a complex plane. The principle of measurement, details of measurement set-up with calibration, testing and limitations observed when applied to solar cells, are presented. To over come the limitations in the measurement set-up, a dedicated userfriendly instrument called Solar Cell Impedance Analyser is developed to measure solar cell AC parameters. It is a personal computer based virtual instrument, which has a power amplifier, a high-speed data acquisition card and an arbitrary function generator card with a custom built micro controller based hardware with an application specific software developed using graphical programming language. A novel concept of software range extender is introduced, which virtually increases the dynamic range of the power amplifier.

Quick evaluation of reservoir performance is a main concern in decision making. Time-consuming input data preparation and computing, along with data uncertainty tend to inhibit the use of numerical reservoir simulators. New analytical solutions are developed for capacitance-resistive models (CRMs) as fast predictive techniques, and their application in history-matching, optimization, and evaluating reservoir uncertainty for water/CO₂ floods are demonstrated. Because the CRM circumvents reservoir geologic modeling and saturation-matching issues, and only uses injection/production rate and bottomhole pressure data, it lends itself to rapid and frequent reservoir performance evaluation. This study presents analytical solutions for the continuity equation using superposition in time and space for three different reservoir-control volumes: 1) entire field volume, 2) volume drained by each producer, and 3) drainage volume between an injector/producer pair. These analytical solutions allow rapid estimation of the CRM unknown parameters: the interwell connectivity and production response time constant. The calibrated model is then combined with oil fractional-flow models for water/CO₂ floods to match the oil production history. Thereafter, the CRM is used for prediction, optimization, flood performance evaluation, and reservoir uncertainty quantification. Reservoir uncertainty quantification is directly obtained from several equiprobable history-matched solutions (EPHMS) of the CRM. We validated CRM's capabilities with numerical flow-simulation results and tested its applicability in several field case studies involving water/CO₂ floods. Development and application of fast, simple and yet powerful analytic tools, like CRMs that only rely on injection and production data, enable rapid reservoir performance evaluation with an acceptable accuracy. Field engineers can quickly obtain significant insights about flood efficiency by estimating interwell connectivities and use the CRM to manage and optimize real time reservoir performance. Frequent usage of the CRM enables evaluation of numerous sets of the EPHMS and consequently quantification of reservoir uncertainty. The EPHMS sets provide good sampling domains and reasonable guidelines for selecting appropriate input data for full-field numerical modeling by evaluating the range and proper combination of uncertain reservoir parameters. Significant engineering and computing time can be saved by limiting numerical simulation input data to the EPHMS sets obtained from the CRMs. / text

The Capacitance Resistance Model (CRM) is a reservoir model based on a data-driven approach. It stems from the continuity equation and takes advantage of the usually abundant rate data to achieve a synergy of analytical model and data-driven approach. Minimal information (rates and bottom-hole pressure) is required to inexpensively characterize the reservoir. Important information, such as inter-well connectivity, reservoir compressibility effects, etc., can be easily and readily evaluated. The model also suggests optimal injection schemes in an effort to maximize ultimate oil recovery, and hence can assist real time reservoir analysis to make more informed management decisions. Nevertheless, an important limitation in the current CRM model is that it only treats the reservoir flow as single-phase flow, which does not favor capturing physics when the saturation change is large, such as for an immature water flood. To overcome this limitation, we develop a two-phase flow coupled CRM model that couples the pressure equation (fluid continuity equation) and the saturation equation (oil mass balance). Through this coupling, the model parameters such as the connectivity, the time constant, temporal oil saturation, etc., are estimated using nonlinear multivariate regression to history match historical production data. Incorporating the physics of two-phase displacement brings several advantages and benefits to the CRM model, such as the estimation of total mobility change, more accurate prediction of oil production, broader model application range, and better adaptability to complicated field scenarios. Also, the estimated saturation within the drainage volume of each producer can provide insights with respect to the field remaining oil saturation distribution. Synthetic field case studies are carried out to demonstrate the different capabilities of the coupled CRM model in homogeneous and heterogeneous reservoirs with different geological features. The physical meanings of model parameters are well explained and validated through case studies. The results validate the coupled CRM model and show improved accuracy in model parameters obtained through the history match. The prediction of oil production is also significantly improved compared to the current CRM model. A more reliable oil rate prediction enables further optimization to adjust injection strategies. The coupled CRM model has been shown to be fast and stable. Moreover, sensitivity analyses are conducted to study and understand the impact of the input information (e.g., relative permeability, viscosity) upon the output model parameters (e.g., connectivity, time constants). This analysis also proves that the model parameters from the two-phase coupled model can combine both reservoir compressibility and mobility effects. / text

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