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Transient simulation for multiscale chip-package structures using the Laguerre-FDTD schemeYi, Ming 21 September 2015 (has links)
The high-density integrated circuit (IC) gives rise to geometrically complex multiscale chip-package structures whose electromagnetic performance is difficult to predict. This motivates this dissertation to work on an efficient full-wave transient solver that is capable of capturing all the electromagnetic behaviors of such structures with high accuracy and reduced computational complexity compared to the existing methods.
In this work, the unconditionally stable Laguerre-FDTD method is adopted as the core algorithm for the transient full-wave solver. As part of this research, skin-effect is rigorously incorporated into the solver which avoids dense meshing inside conductor structures and significantly increases computational efficiency. Moreover, as an alternative to typical planar interconnects for next generation high-speed ICs, substrate integrated waveguide, is investigated. Conductor surface roughness is efficiently modeled to accurately capture its high-frequency loss behavior. To further improve the computational performance of chip-package co-simulation, a novel transient non-conformal domain decomposition method has been proposed. Large-scale chip-package structure can be efficiently simulated by decomposing the computational domain into subdomains with independent meshing strategy. Numerical results demonstrate the capability, accuracy and efficiency of the proposed methods.
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EM simulation using the Laguerre-FDTD scheme for multiscale 3-D interconnectionsHa, Myunghyun 07 November 2011 (has links)
As the current electronic trend is toward integrating multiple functions in a single electronic device, there is a clear need for increasing integration density which is becoming more emphasized than in the past. To meet the industrial need and realize the new system-integration law [1], three-dimensional (3-D) integration is becoming necessary. 3-D integration of multiple functional IC chip/package modules requires co-simulation of the chip and the package to evaluate the performance of the system accurately. Due to large scale differences in the physical dimensions of chip-package structures, the chip-package co-simulation in time-domain using the conventional FDTD scheme is challenging because of Courant-Friedrich-Levy (CFL) condition that limits the time step. Laguerre-FDTD has been proposed to overcome the limitations on the time step. To enhance performance and applicability, SLeEC methodology [2] has been proposed based on the Laguerre-FDTD method. However, the SLeEC method still has limitations to solve practical 3-D integration problems.
This dissertation proposes further improvements of the Laguerre-FDTD and SLeEC method to address practical problems in 3-D interconnects and 3-D integration. A method that increases the accuracy in the conversion of the solutions from Laguerre-domain to time-domain is demonstrated. A methodology that enables the Laguerre-FDTD simulation for any length of time, which was challenging in prior work, is proposed. Therefore, the analysis of the low-frequency response can be performed from the time-domain simulation for a long time period. An efficient method to analyze frequency-domain response using time-domain simulations is introduced. Finally, to model practical structures, it is crucial to model dispersive materials. A Laguerre-FDTD formulation for frequency-dependent dispersive materials is derived in this dissertation and has been implemented.
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