The electromigration (EM) and chip-package interaction (CPI) reliability of flip chip packages with Cu pillar structures was investigated. First the EM-related characteristics of Cu pillars with solder tips were studied and compared with standard controlled collapse chip connection (C4) Pb-free solder joints. The simulation results revealed a significant reduction in the current crowding effect when C4 solder joints was replaced by Cu pillar structures. As a result, the current-induced Joule heating and local temperature gradients were reduced in the Cu pillar structure. This was followed by a study of the impact of the Cu pillar bumps on the mechanical reliability of low-k dielectrics. The CPI-induced crack driving force for delamination in the low-k interconnect structure was evaluated using a 3D sub-modeling technique. The energy release rate was found to increase significantly for packages with Cu pillar bumps compared with those with C4 Pb-free solder joints only. Structural optimization of Cu pillar bumps to improve the mechanical stability of packages with low-k chips was discussed. / text

Surface mount devices (SMDs), such as flip chip packages and ball grid array (BGA) packages are gaining in popularity in microelectronics industry because they provide high density inputs/outputs, better electrical and thermal performance. However, these solder bump interconnections in SMDs are sandwiched between the silicon die and the substrate, which makes them challenging to be inspected. Current non-destructive solder bump inspection techniques like electrical testing, X-ray and acoustic microscopy have some application gaps. New solder bump inspection technique is urgently needed to fill these gaps. Previous work has shown the potential of using a non-contact, non-destructive laser ultrasonics and laser interferometer based inspection system for assessing solder bump qualities. The system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages and a laser interferometer to measure the transient out-of-plane displacement on the package surface. The quality of the solder bumps can be evaluated by analyzing the out-of-plane displacement. However, there are still some gaps that need to be addressed before the system is ready on the shelf. This dissertation focuses on addressing some of these existing issues. The research work consists of the following: 1) a control interface was developed to integrate all the different modules to achieve automation. 2) a new signal-processing method for analyzing the transient out-of-plane displacement signals without requiring a known-good reference chip was developed. 3) the application scope of the system was expanded to inspect the second level solder bumps in BGA packages. Two types of process-induced defects including poor-wetting and solder bump voids were investigated. Meanwhile, solder bump fatigue caused by cyclic mechanical bending and thermal cycle was also studied using this system. 4) a finite element analysis was performed to study the thermo-mechanical reliability of solder bumps in PBGA package under cyclic thermal loads. The successful completion of the research objectives has led to a laser ultrasound solder bump inspection system prototype with more user-friendliness, higher throughputs, better repeatability and more flexibility, which accelerate the commercialization the system.

Advances in microelectronics technology have enabled us to integrate a complex electronic system (such as a radio) on a single chip or in a single package module, known as system-on-chip (SoC) and system-on-package (SoP) paradigms. This brings not only new opportunities for system integration, but also challenges in design and implementation. One of these challenges is how to achieve an optimum total solution of system integration via chip and package co-design, because there is no tool or design methodology available for such kind of optimization. This thesis focuses on innovative multi-band multi-standard radio front-end design and explores a new design methodology. The motivation of developing this design methodology is to achieve an optimum total solution for radio system implementation via chip and package co-design and co-optimization. The methodology starts from RF packaging and components modeling. Necessary models for both on-chip and off-chip passives are developed. Parasitic effects of packages for radio chips are modeled for particular frequencies. Compared with high-speed digital packaging, RF packaging normally deals with narrow band signals. It is possible to absorb some unwanted parasitics by designing proper port matching networks. In addition, cost-performance trade-offs are performed. In this context, we first developed process and technology based cost models, which include parameters like chip real estate, raw materials, package, test and rework. Impact of process variation on final yield has also been considered in the models by using a statistical analysis approach. Performance of different design options is measured by a special FoM (figure-of-merit). Each type of analog/RF circuit (such as LNA, PA and ADC) has its own dedicated FoM. Through a series of cost-performance trade-offs for different on-chip versus off-chip passives and partitions, an optimum total solution is obtained. Finally, this methodology was demonstrated via a number of design examples for multi-band multi-standard radio front-end. The author has explored the optimum solutions for different circuit architectures and process technologies encompassing parallel, concurrent and digitally programmable multi-band radio frond-end blocks. It is interesting to find that, for complex RF circuits like a multi-band multi-standard radio, moving some passives off-chip will have significant cost-savings. In addition to the above contributions, the author has also developed an MCM-D technology on LCP and glass substrates, based on metal deposition and BCB spin-coating at KTH clean room. The author has also performed some preliminary studies on UWB radio for RFID applications. / QC 20101005

QC 20101018

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

This dissertation aims to evaluate the package effects on the performance of radio frequency integrated circuits (RFICs) for wireless applications. A model-based study is presented to compare the effects between flip-chip and wire-bond packages on a front-end cascode low-noise amplifier (LNA) in a 2.45 GHz CMOS wireless local area network (WLAN) receiver. To construct the package electrical models, specific modeling dies are designed to help extract the equivalent-circuit elements from measured S-parameters for chip-package interconnects. Furthermore, the ground-proximity effect on on-chip spiral inductors in a flip-chip package is first observed and presented in this modeling study. Excellent agreement between modeling and measurement is obtained by up to 20 GHz for a 64-pin flip-chip ball grid array (FC-BGA) package and a 64-pin wire-bond quad flat nonlead (WB-QFN) package. For practical applications, the established package models are used to predict the degradation of the figure of merit for the cascode LNA under packaged condition. Chip-package co-simulations can achieve good agreement with measurements, and thus can persuasively account for the complete effects caused by the two different packages on the cascode LNA. To simultaneously consider the package and board interconnect effects on RFICs, this dissertation also designs and implements a 1.95 GHz upconverter for the wideband code-division multiple-access (W-CDMA) transmitter. Specific ground wire-bonding and board connection are designed to minimize the linearity degradation due to package and board interconnects. Nonlinear analysis technique is also used to evaluate the nonlinear distortion of the upconverter in the chip-package-board co-design phase. The final measurement results have successfully verified the co-design predictions and simulations for this upconverter.

No description available.

The high-density integrated circuit (IC) gives rise to geometrically complex multiscale chip-package structures whose electromagnetic performance is difficult to predict. This motivates this dissertation to work on an efficient full-wave transient solver that is capable of capturing all the electromagnetic behaviors of such structures with high accuracy and reduced computational complexity compared to the existing methods. In this work, the unconditionally stable Laguerre-FDTD method is adopted as the core algorithm for the transient full-wave solver. As part of this research, skin-effect is rigorously incorporated into the solver which avoids dense meshing inside conductor structures and significantly increases computational efficiency. Moreover, as an alternative to typical planar interconnects for next generation high-speed ICs, substrate integrated waveguide, is investigated. Conductor surface roughness is efficiently modeled to accurately capture its high-frequency loss behavior. To further improve the computational performance of chip-package co-simulation, a novel transient non-conformal domain decomposition method has been proposed. Large-scale chip-package structure can be efficiently simulated by decomposing the computational domain into subdomains with independent meshing strategy. Numerical results demonstrate the capability, accuracy and efficiency of the proposed methods.

The Internet of Things (IoT) has ushered in an age where low-power sensors generate data which are communicated to a back-end cloud for massive data computation tasks. From the hardware perspective this implies co-existence of several power-efficient sub-systems working harmoniously at the sensor nodes capable of communication and high-speed processors in the cloud back-end. The package-board system-level design plays a crucial role in determining the performance of such low-power sensors and high-speed computing and communication systems. Although there exist several commercial solutions for electromagnetic and circuit analysis and verification, problem diagnosis and design tools are lacking leading to longer design cycles and non-optimal system designs. This work aims at developing methodologies for faster analysis, sensitivity based diagnosis and multi-objective design towards signal integrity and power integrity of such package-board system layouts. The first part of this work aims at developing a methodology to enable faster and more exhaustive design space analysis. Electromagnetic analysis of packages and boards can be performed in time domain, resulting in metrics like eye-height/width and in frequency domain resulting in metrics like s-parameters and z-parameters. The generation of eye-height/width at higher bit error rates require longer bit sequences in time domain circuit simulation, which is compute-time intensive. This work explores learning based modelling techniques that rapidly map relevant frequency domain metrics like differential insertion-loss and cross-talk, to eye-height/width therefore facilitating a full-factorial design space sweep. Numerical results performed with artificial neural network as well as least square support vector machine on SATA 3.0 and PCIe Gen 3 interfaces generate less than 2% average error with order of magnitude speed-up in eye-height/width computation. Accurate power distribution network design is crucial for low-power sensors as well as a cloud sever boards that require multiple power level supplies. Achieving target power-ground noise levels for low power complex power distribution networks require several design and analysis cycles. Although various classes of analysis tools, 2.5D and 3D, are commercially available, the presence of design tools is limited. In the second part of the thesis, a frequency domain mesh-based sensitivity formulation for DC and AC impedance (z-parameters) is proposed. This formulation enables diagnosis of layout for maximum impact in achieving target specifications. This sensitivity information is also used for linear approximation of impedance profile updates for small mesh variations, enabling faster analysis. To enable designing of power delivery networks for achieving target impedance, a mesh-based decoupling capacitor sensitivity formulation is presented. Such an analytical gradient is used in gradient based optimization techniques to achieve an optimal set of decoupling capacitors with appropriate values and placement information in package/boards, for a given target impedance profile. Gradient based techniques are far less expensive than the state of the art evolutionary optimization techniques used presently for a decoupling capacitor network design. In the last part of this work, the functional similarities between package-board design and radio frequency imaging are explored. Qualitative inverse-solution methods common to the radio frequency imaging community, like Tikhonov regularization and Landweber methods are applied to solve multi-objective, multi-variable signal integrity package design problems. Consequently a novel Hierarchical Search Linear Back Projection algorithm is developed for an efficient solution in the design space using piecewise linear approximations. The presented algorithm is demonstrated to converge to the desired signal integrity specifications with minimum full wave 3D solve iterations.