Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging of Cu/low-k chip with organic substrate. The thermo-mechanical deformation and stress develop inside the package during assembly and subsequent reliability tests due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip and the substrate. The thermal residual stress causes many mechanical reliability issues in the solder joints and the underfill layer between die and substrate, such as solder fatigue failure and underfill delamination. Moreover, the thermo-mechanical deformation of the package can be directly coupled into the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The thermo-mechanical reliability risk is further aggravated with the implementation of ultra low-k dielectric for better electrical performance and the mandatory change from Pb-containing solders to Pb-free solders for environmental safety. These CPI-induced reliability issues in flip-chip packaging of Cu/low-k chips are investigated in this dissertation at both chip level and package level using high-resolution Moiré interferometry and Finite Element Analysis (FEA). Firstly, the thermo-mechanical deformation in flip-chip packages is analyzed using high-resolution Moiré interferometry. The effect of underfill properties on package warpage is studied and followed by a strategy study of proper underfill selection to improve solder fatigue life time and reduce the risk of interfacial delamination in underfill and low-k interconnects under CPI. The chip-package interaction is found to maximize at the die attach step during assembly and becomes most detrimental to low-k chip reliability because of the high thermal load generated by the solder reflow process before underfilling. A three-dimensional (3D) multilevel sub-modeling method combined with modified virtual crack closure (MVCC) technique is employed to investigate the CPI-induced interfacial delamination in Cu/low-k interconnects. It is first focused on the effects of dielectrics and solder materials on low-k interconnect reliability and then extended to the scaling effect where the reduction of the interconnect dimension is accompanied with an increased number of metal levels and the implementation of ultralow-k porous dielectrics. Recent studies on CPI-induced crack propagation in the low-k interconnect and the use of crack-stop structures to improve the chip reliability are also discussed. Finally, 3D integration (3DI) with through silicon vias (TSV) has been proposed as the latest solution to increase the device density without down-scaling. The thermo-mechanical reliability issues facing 3DI are analyzed. Three failure modes are proposed and studied. Design optimization of 3D interconnects to reduce the thermal residual stress and the risks of fracture and delamination are discussed. / text

Electromigration (EM) and thermomigration (TM) reliability of Pb-free solder joints are emerging as critical concerns in advanced packages. In this study, EM and TM phenomena in Sn-2.5Ag solder joints with thick Cu or thin Ni under-bump metallurgy (UBM) were investigated. A series of EM tests were performed to obtain activation energy (Q) and current density exponent (n), and to understand failure mechanisms. Joule heating was also taken into account. Q and n values were determined as follows: for Cu UBM solders, Q = 1.0 eV and n = 1.5; for Ni UBM solders, Q = 0.9 and n = 2.2. Important factors limiting EM reliability of Pb-free solder joints were found to be UBM dissolution with extensive intermetallic compound (IMC) growth and current crowding. IMC growth without current stressing was found to follow the parabolic growth law whereas linear growth law was observed for Cu₆Sn₅ and Ni₃Sn₄ under high current stressing. For Cu UBM solders, the apparent activation energy for IMC growth was consistent with the activation energy for EM, which supports that EM failure was closely related to IMC growth. In contrast, for Ni UBM solders the apparent activation energy was higher than the EM activation energy. It was suggested that the EM failure in the Ni UBM solders could be associated with more than one mass transport mechanism. The current crowding effect was analyzed with different thicknesses of Ni UBM. It was found that the maximum current density in solder could represent the current density term in Black's equation better than the average current density. FEM studies demonstrated that current crowding was mainly controlled by UBM thickness, metal trace design, and passivation opening diameter. A large temperature gradient of the order of 10³ °C/cm was generated across the sample to induce noticeable TM and to compare its effect against that of EM. TM-induced voiding was observed in Ni UBM solders while UBM dissolution with IMC formation occurred in Cu UBM solders. However, the relative effect of TM was found to be several times smaller than that of EM even at this large temperature gradient. / text

The goal of this thesis is to work out an introduction to the chip packaging and decapsulation. Further can be found a description of a method leading to dacapsulate concrete chips. Final part is devoted to getting chip pictures using microscope and analysis of the pictures afterwards.

The demands of consumer electronic products to support multi-functionality such as computing, communication and multimedia applications with reduced form factor and low cost is the driving force behind packaging technologies such as System on Package (SOP). SOP aims to enhance the functionality of the package while providing form factor reduction by the integration of active and passive components. However, embedding components within mixed signal packages causes unwanted interferences across the digital and analog-radio frequency (RF) sections of the package, which is a major challenge yet to be addressed. This dissertation focused on the chip-last method of embedding chips within cavities in organic packages and addressed the challenges for preserving power integrity in such packages. The challenges associated with electromagnetic coupling in packages when chips are embedded within the substrate layers are identified, analyzed and demonstrated. The presence of the chip embedded within the package introduces new interaction mechanisms between the chip and package that have not been encountered in conventional packages with surface mounted chips. It is of significant importance to understand the chip-package interaction mechanisms, for ensuring satisfactory design of systems with embedded actives. The influence of the electromagnetic coupling from the package on the bulk substrate and bond-pads of the embedded chip are demonstrated. Solutions that remedy the noise coupling using Electromagnetic Band-Gap structures (EBGs) along with design methodologies for their efficient implementation in multilayer packages are proposed. This dissertation presents guidelines for designing efficient power distribution networks in multilayer packages with embedded chips.

The objective of this dissertation is to derive a set of compact physical models addressing power integrity issues in high performance gigascale integration (GSI) systems and three-dimensional (3-D) systems. The aggressive scaling of CMOS integrated circuits makes the design of power distribution networks a serious challenge. This is because the supply current and clock frequency are increasing, which increases the power supply noise. The scaling of the supply voltage slowed down in recent years, but the logic on the integrated circuit (IC) still becomes more sensitive to any supply voltage change because of the decreasing clock cycle and therefore noise margin. Excessive power supply noise can lead to severe degradation of chip performance and even logic failure. Therefore, power supply noise modeling and power integrity validation are of great significance in GSI systems and 3-D systems. Compact physical models enable quick recognition of the power supply noise without doing dedicated simulations. In this dissertation, accurate and compact physical models for the power supply noise are derived for power hungry blocks, hot spots, 3-D chip stacks, and chip/package co-design. The impacts of noise on transmission line performance are also investigated using compact physical modeling schemes. The models can help designers gain sufficient physical insights into the complicated power delivery system and tradeoff various important chip and package design parameters during the early stages of design. The models are compared with commercial tools and display high accuracy.

Cette thèse porte sur la caractérisation, la modélisation et l'analyse des phénomènes de «Pulling» et de «Pushing» dans les systèmes de boucles à verrouillage de phase (PLL), utilisant une approche globale où les effets de couplages électromagnétiques aux différents niveaux d'intégration (niveau puce, niveau assemblage, niveau report sur PCB) sont pris en compte de manière distribuée. L'approche de modélisation adopte une méthodologie hybride où l'analyse des couplages électromagnétiques combinée à des schémas équivalents large-bande (compatibles avec les modèles de composants actifs disponibles dans les librairies) est couplée à des représentations comportementales dynamiques. Les représentations comportementales développées permettent de capturer des effets de non-linéarités tant au niveau composant (caractéristique non-linéaire des Varicap en fonction des tensions de contrôle) qu'au niveau block de fonction (gain KVCO non uniforme de l'oscillateur contrôlé en tension (VCO) en fonction de la fréquence).Cette méthodologie hybride permet l'évaluation d'effets compétitifs résultant de phénomènes de «pulling» et de «Pushing» au niveau de la puce (influence de la PLL, effets de l'amplificateur de puissance, intégrité des alimentations ou distribution des références de masse, etc.) , et des distorsions induites par des éléments extérieurs à la puce (exemple de composants sur PCB : Filtre SAW, capacités de découplages, réseaux d'adaptation).L'approche proposée est utilisée pour l'étude et la conception de deux types de circuits développés par NXP-semi-conducteurs pour des applications liées à la sécurité automobile (PLL fonctionnant aux alentours de 1.736GHz) et à la réception satellitaire (PLL de faible consommation fonctionnant à 9.75/10.6 GHz pour les circuits LNB).Les résultats de modélisation obtenus sont validés par corrélations avec les données expérimentales et par comparaison avec les résultats obtenus de différents outils (ADS Harmonic- Balance/Transient de Agilent, Spectre de Cadence / This thesis work focuses on characterization, modeling and analysis of «Pulling» and «Pushing» phenomena in Phase Locked Loops (PLL) based on a global approach where distributed effects of electromagnetic couplings at different integration levels (chip-level, assembly-level, board or PCB-level) are taken into account. The modeling approach adopts a hybrid methodology where the analysis of electromagnetic couplings combined with broadband equivalent circuit synthesis (compatible with library models of active components) is coupled with dynamic behavioral representations. The derived behavioral representations properly capture the effects of nonlinearities both at component scale (non-linear characteristic of varicap as function of control voltages) and at function block level (non-uniform gain KVCO of VCO circuits depending on frequency).The hybrid methodology renders possible the assessment of competitive effects resulting from «Pulling» and «Pushing» phenomena at chip level (influence of the PLL, effects of the power amplifier, power integrity, or ground reference distribution, etc..), and the distortions induced by components external to the chip at package and board levels (such as components on PCB: SAW filters, decoupling capacitors, matching networks).The proposed approach is used for the study and design of two types of circuits developed by NXP- Semiconductors, for applications related to automotive security and immobilization (an RF low power transceiver Integrated Circuit (PLL running around 1.763GHz), and to satellite receiver (PLL operating at low power for LNB circuits working at 9.75/10.6 GHz).The obtained modeling results are validated by correlation with experimental data and by comparison with different time-domain and frequency-domain simulation tools results (ADS-Harmonic Balance, ADS-Shooting solutions, Cadence-Spectre)