The demand for high performance microelectronic products drives the development of 3-D chip-stacking structure. By the introduction of through-silicon-via (TSV) into 3-D flip-chip packages, microelectronic performance is improved by increasing circuit capacity and diminishing signal delay. However, TSV-embedded structure also raises concerns over many reliability issues that come with the steep thermal and mechanical transient responses, increasing numbers of bi-material interfaces and reduced component sizes. In this research, defect initiation induced by thermalmechanical phenomena is studied to establish the early failure modes within 3-D flip-chip packages. It is found that low amplitude but extremely high frequency thermal stress waves would occur and attenuate rapidly in the first hundreds of nanoseconds upon power-on. Although the amplitude of these waves is far below material yielding points, their intrinsic characteristics of high frequency and high power density are capable of compromising the integrity of all flip-chip components. By conducting spectral analysis of the stress waves and applying the methodology of accumulated damage evaluation, it is demonstrated that micron crack initiation and interconnect debond are highly probable in the immediate proximity of the heat source. Such a negative impact exerted by the stress wave in the early, while brief, transient period is recognized as the short time scale dynamic effect. Researched results strongly indicate that short-time scale effects would inflict very serious reliability issues in 3-D flip-chip packages. The fact that 3-D flip-chip packages accommodate a large amount of reduced-size interconnects makes it vulnerable to the attack of short time scale propagating stress waves. In addition, the stacking structure also renders shearing effect extremely detrimental to 3-D flip-chip integrity. Finally, several guidelines effective in discouraging short-time scale effects and thus improving TSV flip-chip package reliability are proposed

As the trend of miniaturization of complex integrated circuit(IC) devices, the current density of flip-chip solder bumps have increased significantly and each solder joint is supporting a current density close to or even over 104 A/cm2 .Therefore, in SnPb eutectic solder, which has a high diffusivity at the operating temperature due to its low melting point, the electromigration becomes a major reliability threat. Thus, the thesis is aimed to investigate the effects of electromigration behavior on flip-chip package eutectic Sn-Pb solder bumps reliability under high current density. The current densities are 2x104 A/cm2 and 1.5x104 A/cm2,the surface of die temperatures are 115¢Jand 95¢J.The bump temperature, the histories of the bump resistance, and mean time to failure (MTTF) testings were conducted. The failure mechanism was observed through SEM and EDS. From the results of the experiment, the dominant failure mode of the bump is due to electromigration behavior that causes voids at UBM/bump interface (cathode) when the sample¡¦s failure time is shorter. As the failure time is longer, the failure is also resulted from heat effect in addition to electromigration behavior.

This dissertation aims to evaluate the package effects on the performance of radio frequency integrated circuits (RFICs) for wireless applications. A model-based study is presented to compare the effects between flip-chip and wire-bond packages on a front-end cascode low-noise amplifier (LNA) in a 2.45 GHz CMOS wireless local area network (WLAN) receiver. To construct the package electrical models, specific modeling dies are designed to help extract the equivalent-circuit elements from measured S-parameters for chip-package interconnects. Furthermore, the ground-proximity effect on on-chip spiral inductors in a flip-chip package is first observed and presented in this modeling study. Excellent agreement between modeling and measurement is obtained by up to 20 GHz for a 64-pin flip-chip ball grid array (FC-BGA) package and a 64-pin wire-bond quad flat nonlead (WB-QFN) package. For practical applications, the established package models are used to predict the degradation of the figure of merit for the cascode LNA under packaged condition. Chip-package co-simulations can achieve good agreement with measurements, and thus can persuasively account for the complete effects caused by the two different packages on the cascode LNA. To simultaneously consider the package and board interconnect effects on RFICs, this dissertation also designs and implements a 1.95 GHz upconverter for the wideband code-division multiple-access (W-CDMA) transmitter. Specific ground wire-bonding and board connection are designed to minimize the linearity degradation due to package and board interconnects. Nonlinear analysis technique is also used to evaluate the nonlinear distortion of the upconverter in the chip-package-board co-design phase. The final measurement results have successfully verified the co-design predictions and simulations for this upconverter.

Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging of Cu/low-k chip with organic substrate. The thermo-mechanical deformation and stress develop inside the package during assembly and subsequent reliability tests due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip and the substrate. The thermal residual stress causes many mechanical reliability issues in the solder joints and the underfill layer between die and substrate, such as solder fatigue failure and underfill delamination. Moreover, the thermo-mechanical deformation of the package can be directly coupled into the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The thermo-mechanical reliability risk is further aggravated with the implementation of ultra low-k dielectric for better electrical performance and the mandatory change from Pb-containing solders to Pb-free solders for environmental safety. These CPI-induced reliability issues in flip-chip packaging of Cu/low-k chips are investigated in this dissertation at both chip level and package level using high-resolution Moiré interferometry and Finite Element Analysis (FEA). Firstly, the thermo-mechanical deformation in flip-chip packages is analyzed using high-resolution Moiré interferometry. The effect of underfill properties on package warpage is studied and followed by a strategy study of proper underfill selection to improve solder fatigue life time and reduce the risk of interfacial delamination in underfill and low-k interconnects under CPI. The chip-package interaction is found to maximize at the die attach step during assembly and becomes most detrimental to low-k chip reliability because of the high thermal load generated by the solder reflow process before underfilling. A three-dimensional (3D) multilevel sub-modeling method combined with modified virtual crack closure (MVCC) technique is employed to investigate the CPI-induced interfacial delamination in Cu/low-k interconnects. It is first focused on the effects of dielectrics and solder materials on low-k interconnect reliability and then extended to the scaling effect where the reduction of the interconnect dimension is accompanied with an increased number of metal levels and the implementation of ultralow-k porous dielectrics. Recent studies on CPI-induced crack propagation in the low-k interconnect and the use of crack-stop structures to improve the chip reliability are also discussed. Finally, 3D integration (3DI) with through silicon vias (TSV) has been proposed as the latest solution to increase the device density without down-scaling. The thermo-mechanical reliability issues facing 3DI are analyzed. Three failure modes are proposed and studied. Design optimization of 3D interconnects to reduce the thermal residual stress and the risks of fracture and delamination are discussed. / text