As the trend of miniaturization of complex integrated circuit(IC) devices, the current density of flip-chip solder bumps have increased significantly and each solder joint is supporting a current density close to or even over 104 A/cm2 .Therefore, in SnPb eutectic solder, which has a high diffusivity at the operating temperature due to its low melting point, the electromigration becomes a major reliability threat. Thus, the thesis is aimed to investigate the effects of electromigration behavior on flip-chip package eutectic Sn-Pb solder bumps reliability under high current density. The current densities are 2x104 A/cm2 and 1.5x104 A/cm2,the surface of die temperatures are 115¢Jand 95¢J.The bump temperature, the histories of the bump resistance, and mean time to failure (MTTF) testings were conducted. The failure mechanism was observed through SEM and EDS. From the results of the experiment, the dominant failure mode of the bump is due to electromigration behavior that causes voids at UBM/bump interface (cathode) when the sample¡¦s failure time is shorter. As the failure time is longer, the failure is also resulted from heat effect in addition to electromigration behavior.

This thesis presents the low cost process for UBM formation on aluminum pads of single die/dice for Flip Chip applications. The UBM (Under Bump Metallurgy) is required in solder bump structure to provide adhesion/diffusion barrier layer, solder wettable layer, and oxidation barrier layer between the bonding pads of the die and the bumps. Typically, UBM is deposited on the whole wafers by sputtering, evaporation, or electroless plating. These deposition techniques are not practical for UBM formation on single die/dice, thus preventing Flip Chip technology to be applied in applications where the whole wafers are not available. The process presented in this thesis has been developed to overcome this problem. The developed UBM formation process allows the UBM layer to be deposited on a single die, thus eliminating the requirement to have the whole wafer in the deposition process. With the combination of the UBM formation process developed in this work and a suitable bump formation technique, solder bumping on a single die can be achieved, thus making Flip Chip technology available for use in low volume applications and prototyping stages. The developed UBM formation process consists of two major steps; temporary die attach process and UBM deposition process. The first process is developed using thermoplastic adhesive film. The second process is developed using electroless nickel plating, followed by gold immersion. It has been demonstrated in this thesis that the developed process can be used to form the UBM layer on the die successfully regardless of the die size and the complexity of the die pattern, and that this process does not damage nor affect electrically the sensitive die. / Master of Science

Surface mount devices (SMDs), such as flip chip packages and ball grid array (BGA) packages are gaining in popularity in microelectronics industry because they provide high density inputs/outputs, better electrical and thermal performance. However, these solder bump interconnections in SMDs are sandwiched between the silicon die and the substrate, which makes them challenging to be inspected. Current non-destructive solder bump inspection techniques like electrical testing, X-ray and acoustic microscopy have some application gaps. New solder bump inspection technique is urgently needed to fill these gaps. Previous work has shown the potential of using a non-contact, non-destructive laser ultrasonics and laser interferometer based inspection system for assessing solder bump qualities. The system uses a pulsed Nd:YAG laser to induce ultrasound in the chip packages and a laser interferometer to measure the transient out-of-plane displacement on the package surface. The quality of the solder bumps can be evaluated by analyzing the out-of-plane displacement. However, there are still some gaps that need to be addressed before the system is ready on the shelf. This dissertation focuses on addressing some of these existing issues. The research work consists of the following: 1) a control interface was developed to integrate all the different modules to achieve automation. 2) a new signal-processing method for analyzing the transient out-of-plane displacement signals without requiring a known-good reference chip was developed. 3) the application scope of the system was expanded to inspect the second level solder bumps in BGA packages. Two types of process-induced defects including poor-wetting and solder bump voids were investigated. Meanwhile, solder bump fatigue caused by cyclic mechanical bending and thermal cycle was also studied using this system. 4) a finite element analysis was performed to study the thermo-mechanical reliability of solder bumps in PBGA package under cyclic thermal loads. The successful completion of the research objectives has led to a laser ultrasound solder bump inspection system prototype with more user-friendliness, higher throughputs, better repeatability and more flexibility, which accelerate the commercialization the system.

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

Flip-chip underfilling is a technology by which silica-filled epoxy resin is used to fill the micro-cavity between a silicon chip and a substrate, by dispensing the liquid encapsulant at elevated temperatures along the periphery of one or two sides of the chip and then allowing capillary action to draw the material into the gap. Since the chip, underfill material, and substrate solidify together as one unit, thermal stresses on solder joints during the temperature cycling (which are caused by a mismatch in the coefficients of thermal expansion between the silicon chip and the organic substrate) can be redistributed and transferred away from the fragile bump zone to a more strain-tolerant region. Modeling of the flow behaviour of a fluid in the underfill process is the key to this technology. One of the most important drawbacks in the existing models is inadequate treatment of non-Newtonian fluids in the underfill process in the development of both analytical models and numerical models. Another important drawback is the neglect of the presence of solder bumps in the existing analytical models. This thesis describes a study in which a proper viscosity constitutive equation, power-law model, is employed for describing the non-Newtonian fluid behaviour in flip-chip package. Based on this constitutive equation, two analytical models with closed-form solutions for predicting the fluid filling time and fluid flow front position with respect to time were derived. One model is for a setting with two parallel plates as an approximate to flip-chip package, while the other model is for a setting with two parallel plates within which an array of solder bumps are present. Furthermore, a numerical model using a general-purpose finite element package ANSYS was developed to predict the fluid flow map in two dimensions. The superiority of these models to the existing models (primarily those developed at Cornell University in 1997) is confirmed based on the results of the experiments conducted in this study. This thesis also presents a finding of the notion of critical clearance in the design of a flip-chip package through a careful simulation study using the models developed. The flip-chip package design should make the clearance between solder bumps larger than the critical clearance.

Consumer demands are driving the current trend in the microelectronics industry to make electronic products that are miniature, fast, compact, high-density, reliable and low-cost. The use of surface mount devices (SMDs) has helped to decrease the size of electronic packages through the use of solder bump interconnections between the devices and the substrates/printed wiring boards (PWBs). Solder bumps act as not only mechanical, but also electrical interconnections between the device and the substrate/PWB. Common manufacturing defects ¨C such as open, cracked, missing, and misaligned solder bumps ¨C are difficult to detect because solder bumps are hidden between the device and the substrate/PWB after assembly. The reliability of packaged electronic devices in storage and usage is a major concern in the microelectronics industry. Therefore, quality inspection of solder bumps has become a critical process in the microelectronics industry to help ensure product quality and reliability. In this thesis, a methodology for quality evaluation and reliability study of solder bumps in electronic packages has been developed using the non-destructive and non-contact laser ultrasound-interferometric technique, finite element and statistical methods in this research work. This methodology includes the following aspects: 1) inspection pattern ¨C specific inspection patterns are created according to inspection purpose and package formats, 2) laser pulse energy density calibration ¨C specific laser pulse power and excitation laser spot size are selected in terms of package formats, 3) processing and analysis methods, including integrated analytical, finite element and experimental modal analyses approach, advanced signal processing methods and statistical analysis method, 4) approach combining modal analysis and advanced signal processing to improve measurement sensitivity of laser ultrasound-interferometric inspection technique, and 5) calibration curve using energy based simulation method and laser ultrasound inspection technique to predict thermomechanical reliability of solder bumps in electronic packages. Because of the successful completion of the research objectives, the system has been used to evaluate a broad range of solder bump defects in a variety of packaged electronic devices. The development of this system will help tremendously to improve the quality and reliability of electronic packages.

This thesis examines the packaging of high-temperature SiC power electronic devices. Current-voltage measurements were conducted on as-received and packaged SiC power devices. The planar structure was introduced and developed as a substitution for traditional wire-bonding vertical structure. The planar structure was applied to a high temperature (>250oC) SiC power device. Based on the current-voltage (I-V) measurements, the packaging structures were improved, materials were selected, and processes were tightly controlled. This study applies two types of planar structures, the direct bond and the bump bond, to the high-temperature packaging of high-temperature SiC diode. A drop in the reverse breakdown voltage was discovered in the packaging using a direct bond. The root cause for the drop in the breakdown voltage was identified and corrective solutions were evaluated. A few effective methods were suggested for solving the breakdown issue. The forward I-V curve of the planar packaging using direct bond showed excellent results due to the excellent electrical and thermal properties of sintered nanosilver. The packaging using a bump bond as an improved structure was processed and proved to possess desirable forward and reverse I-V behavior. The cross-sections of both planar structures were inspected. High-temperature packaging materials, including nano-silver paste, high-lead solder ball and paste, adhesive epoxy, and encapsulant, were introduced and evaluated. The processes such as stencil printing, low-temperature sintering, solder reflowing, epoxy curing, sputtering deposition, electroplating, and patterning of direct-bond copper (DBC) were tightly controlled to ensure high-quality packaging with improved performance. Finally, the planar packaging of the high temperature power device was evaluated and summarized, and the future work was recommended. / Master of Science

Out-of-plane displacement (warpage) is one of the major thermomechanical reliability concerns for board-level electronic packaging. Printed wiring board (PWB) and component warpage results from CTE mismatch among the materials that make up the PWB assembly (PWBA). Warpage occurring during surface-mount assembly reflow processes and normal operations may cause serious reliability problems. In this research, a convective reflow and projection moire warpage measurement system was developed. The system is the first real-time, non-contact, and full-field measurement system capable of measuring PWB/PWBA/chip package warpage with the projection moire technique during different thermal reflow processes. In order to accurately simulate the reflow process and to achieve the ideal heating rate, a convective heating system was designed and integrated with the projection moire system. An advanced feedback controller was implemented to obtain the optimum heating responses. The developed system has the advantages of simulating different types of reflow processes, and reducing the temperature gradients through the PWBA thickness to ensure that the projection moire system can provide more accurate measurements. Automatic package detection and segmentation algorithms were developed for the projection moire system. The algorithms are used for automatic segmentation of the PWB and assembled packages so that the warpage of the PWB and chip packages can be determined individually. The effect of initial PWB warpage on the fatigue reliability of solder bumps on board assemblies was investigated using finite element modeling (FEM) and the projection moire system. The 3-D models of PWBAs with varying board warpage were used to estimate the solder bump fatigue life for different chip packages mounted on PWBs. The simulation results were validated and correlated with the experimental results obtained using the projection moire system and accelerated thermal cycling tests. Design of experiments and an advanced prediction model were generated to predict solder bump fatigue life based on the initial PWB warpage, package dimensions and locations, and solder bump materials. This study led to a better understanding of the correlation between PWB warpage and solder bump thermomechanical reliability on board assemblies.

Complex structures and multiple interfaces of modern microelectronic packages complicate the interpretation of acoustic data. This study has four novel contributions. 1) Contributions to the finite element method. 2) Novel approaches to reduce computational cost. 3) New post processing technologies to interpret the simulation data. 4) Formation of theoretical guidance for acoustic image interpretation. The impact of simulation resolution on the numerical dispersion error and the exploration of quadrilateral infinite boundaries make up the first part of this thesis's contributions. The former focuses on establishing the convergence score of varying resolution densities in the time and spatial domain against a very high fidelity numerical solution. The latter evaluates the configuration of quadrilateral infinite boundaries in comparison against traditional circular infinite boundaries and quadrilateral Perfectly Matched Layers. The second part of this study features the modelling of a flip chip with a 140µm solder bump assembly, which is implemented with a 230MHz virtual raster scanning transducer with a spot size of 17µm. The Virtual Transducer was designed to reduce the total numerical elements from hundreds of millions to hundreds of thousands. Thirdly, two techniques are invented to analyze and evaluate simulated acoustic data: 1) The C-Line plot is a 2D max plot of specific gate interfaces that allows quantitative characterization of acoustic phenomena. 2) The Acoustic Propagation Map, contour maps an overall summary of intra sample wave propagation across the time domain in one image. Lastly, combining all the developments. The physical mechanics of edge effects was studied and verified against experimental data. A direct relationship between transducer spot size and edge effect severity was established. At regions with edge effect, the acoustic pulse interfacing with the solder bump edge is scattered mainly along the horizontal axis. The edge effect did not manifest in solder bump models without Under Bump Metallization (UBM). Measurements found acoustic penetration improvements of up to 44% with the removal of (UBM). Other acoustic mechanisms were also discovered and explored. Defect detection mechanism was investigated by modelling crack propagation in the solder bump assembly. Gradual progression of the crack was found have a predictable influence on the edge effect profile. By exploiting this feature, the progress of crack propagation from experimental data can be interpreted by evaluating the C-Scan image.