Multilayer embedded passives (resistors, inductors, and capacitors) on a printed wiring board can help to meet high performance requirements at a low cost and at a smaller size. Such an integration of embedded passives has new challenges with respect to design, materials, manufacturing, thermal management and reliability. As the area of integral passives on printed circuit boards is relatively new, there is inadequate literature on the thermo-mechanical reliability of integral passives. Therefore, there is a compelling need to understand the thermo-mechanical reliability of integral passives through the development of physics-based models as well as through experiments, and this thesis aims to develop such an experimental and theoretical program to study the thermo-mechanical reliability of integral passives.. As integral passives are often composite layers with dissimilar material properties compared to the other layers in the integral substrate, it is essential to ensure that RLC characteristics of the embedded passives do not deteriorate with thermal cycling due to thermo-mechanical deformations. This thesis aims to study the changes in the passive characteristics due to the thermally-induced deformations. Embedded capacitors and inductors have been looked at specifically in this research. Multi-field physics-based models have been constructed to determine the change in electrical parameters after thermal cycling. The thermo-mechanical models assume direction-dependent material properties for the board substrate and interconnect copper layers and temperature-dependent properties for interlayer dielectric and passive layers. Using the deformed geometry, the electrical characteristics have been determined at low frequency. In parallel to the models, test vehicle substrates have been subjected to 1000 thermal cycles between -55??o 125??nd high humidity and temperature conditions at 85??5RH for 500 hours, and it has been observed that there are significant changes in the electrical parameters. The results obtained from the physics-based simulations have been validated against the measured electrical characteristics from the fabricated functional test boards that have been thermal cycled.

Chip-package interaction (CPI) has become a critical reliability issue for flip-chip packaging of Cu/low-k chip with organic substrate. The thermo-mechanical deformation and stress develop inside the package during assembly and subsequent reliability tests due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip and the substrate. The thermal residual stress causes many mechanical reliability issues in the solder joints and the underfill layer between die and substrate, such as solder fatigue failure and underfill delamination. Moreover, the thermo-mechanical deformation of the package can be directly coupled into the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The thermo-mechanical reliability risk is further aggravated with the implementation of ultra low-k dielectric for better electrical performance and the mandatory change from Pb-containing solders to Pb-free solders for environmental safety. These CPI-induced reliability issues in flip-chip packaging of Cu/low-k chips are investigated in this dissertation at both chip level and package level using high-resolution Moiré interferometry and Finite Element Analysis (FEA). Firstly, the thermo-mechanical deformation in flip-chip packages is analyzed using high-resolution Moiré interferometry. The effect of underfill properties on package warpage is studied and followed by a strategy study of proper underfill selection to improve solder fatigue life time and reduce the risk of interfacial delamination in underfill and low-k interconnects under CPI. The chip-package interaction is found to maximize at the die attach step during assembly and becomes most detrimental to low-k chip reliability because of the high thermal load generated by the solder reflow process before underfilling. A three-dimensional (3D) multilevel sub-modeling method combined with modified virtual crack closure (MVCC) technique is employed to investigate the CPI-induced interfacial delamination in Cu/low-k interconnects. It is first focused on the effects of dielectrics and solder materials on low-k interconnect reliability and then extended to the scaling effect where the reduction of the interconnect dimension is accompanied with an increased number of metal levels and the implementation of ultralow-k porous dielectrics. Recent studies on CPI-induced crack propagation in the low-k interconnect and the use of crack-stop structures to improve the chip reliability are also discussed. Finally, 3D integration (3DI) with through silicon vias (TSV) has been proposed as the latest solution to increase the device density without down-scaling. The thermo-mechanical reliability issues facing 3DI are analyzed. Three failure modes are proposed and studied. Design optimization of 3D interconnects to reduce the thermal residual stress and the risks of fracture and delamination are discussed. / text