This dissertation proposed a novel time-domain algorithm for extracting the broadband SPICE-compatible models of power/ground planes with resonance effect. The time-domain algorithm approach can focus on the modeling of interconnectors and power/ground planes based on a broadband macro model. Every module of the broadband macro model is represented by the optimum pole-residue forms. Using a systematic lumped-model extraction technique, all the optimum pole-residue rational functions can be transferred into a corresponding lumped circuit model. The accuracy of the time-domain algorithms is demonstrated both in time- and frequency-domain responses comparison by the 3D-FDTD simulation and measurement. In addition, these models can be efficiently incorporated into the currently available circuit simulator such as HSpice for the consideration of power/ground bouncing noise with active devices in high-speed circuits.

Advancements in very large scale integration (VLSI) technology have led to unprecedented transistor and interconnect scaling. Further miniaturization by traditional IC scaling in future planar CMOS technology faces significant challenges. Stacking of ICs (3D IC) using three dimensional (3D) integration technology helps in significantly reducing wiring lengths, interconnect latency and power dissipation while reducing the size of the chip and enhancing performance. Interposer technology with ultra-fine pitch interconnections needs to be developed to support the huge I/O connection requirement for packaging 3D ICs. Through vias in stacked silicon ICs and interposers are the key components of a 3D system. The objective of this dissertation is to model through vias in 3D silicon and glass interposers and, to address power and high-speed signal integrity issues in 3D interposers considering silicon biasing effects. An equivalent circuit model of the through via in silicon interposer (Si TPV) has been proposed considering the bias voltage dependent Metal-Oxide-Semiconductor (MOS) capacitance effect. Important design guidelines and optimizations are proposed for Si TPVs used in the signal delivery network, power delivery network (PDN), and as variable capacitors. Through vias in glass interposers (Glass TPVs) are modeled, designed and simulated by using electromagnetic field solvers. Signal and power integrity analyses are performed for silicon and glass interposers. PDN design is proposed by utilizing the MOS capacitance of the Si TPVs for decoupling.

Effective power delivery in Double-sided 3-D glass interposer packages was proposed, investigated, and demonstrated towards achieving high logic-to-memory bandwidth. Such 3-D interposers enable a simpler alternative to direct 3-D stacking by providing low-loss, wide-I/O channels between the logic device on one side of the ultra-thin glass interposer and memory stack on the other side, eliminating the need for complex TSVs in the logic die. A simplified PDN design approach with power-ground planes was proposed to overcome resonance challenges from (a) added parasitic inductance in the lateral power delivery path from the printed wiring board (PWB), due to die placement on the bottom side of the interposer, and (b) the low-loss property of the glass substrate. Based on this approach, this dissertation developed three important suppression solutions using, (a) the 3-D interposer package configuration, (b) the selection of embedded and SMT-based decoupling capacitors, and (c) coaxial power-ground planes with TPVs. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board (PWB) and chip-level models. Two-metal and four-metal layer test vehicles were fabricated on 30-μm and 100-μm thick glass substrates using a panel-based double-side fabrication process, for potential lower cost and improved electrical performance. The PDN test structures were characterized upto 20 GHz, to demonstrate the measured verification of (a) 3-D glass interposer power delivery network and (b) resonance suppression. The data and analysis presented in this dissertation prove that the objectives of this research were met successfully, leading to the first demonstration of effective PDN design in ultra-thin (30-100μm), and 3-D double-sided glass BGA packages, by suppressing the PDN noise from mode resonances.

As the complexity of interconnects and packages increases and the rise and fall time of the signal decreases, the electromagnetic effects of distributed passive devices are becoming an important factor in determining the performance of gigahertz systems. The electromagnetic behavior extracted using an electromagnetic simulation or from measurements is available as frequency dependent data. This information can be represented as a black box called a macromodel, which captures the behavior of the passive structure at the input/output ports. In this dissertation, the macromodels have been categorized as scalable, passive and broadband macromodels. The scalable macromodels for building design libraries of passive devices have been constructed using multidimensional rational functions, orthogonal polynomials and selective sampling. The passive macromodels for time-domain simulation have been constructed using filter theory and multiport passivity formulae. The broadband macromodels for high-speed simulation have been constructed using band division, selector, subband reordering, subband dilation and pole replacement. An automated construction method has been developed. The construction time of the multiport macromodel has been reduced. A method for reducing the order of the macromodel has been developed. The efficiency of the methods was demonstrated through embedded passive devices, known transfer functions and distributed interconnect networks.

As microprocessors move towards higher frequencies, lower operating voltages and higher power consumption, supplying noise-free power to the ICs becomes increasingly challenging. Decoupling capacitors with low inductance interconnections are critical to meet the power supply impedance targets. A variety of capacitors are used today to provide decoupling at different frequencies. Surface-mount multi-layer ceramic capacitors currently used at package level provide decoupling only till about 100 MHz because of the component and lead inductances. Embedding thin film capacitors into the package can expand the operating range of package level capacitors to low GHz frequencies. Thin films with capacitance of several microfarads and organic-compatible processes are required for embedding decoupling capacitors at package level. The organic-compatible high-permittivity materials available today do not provide adequate capacitance for the application on hand. While ferroelectric thin films can provide the required capacitance, processing temperatures over 300o C are required to achieve crystalline films with high permittivity. Hence, there is a need to develop novel materials and processes to integrate decoupling capacitors into currently prevalent organic packages. To this end, hydrothermal synthesis and sol-gel synthesis of BaTiO3 films were explored in this study. BaTiO3 films were synthesized by low temperature hydrothermal conversion of metallic titanium. Hydrothermal process parameters such as bath molarity and temperature were optimized to obtain thin films with grain sizes close to 100 nm, at temperatures less than 100o C. Novel post-hydrothermal treatments were developed to improve the dielectric properties of the films. Sol-gel process requires sintering at >700o C to obtain crystalline BaTiO3 films. However, the films can be synthesized on free-standing copper foils and subsequently integrated into organic packages using lamination. Prevention of foil oxidation during sintering is critical. Nickel and titanium barriers explored in this study were ineffective due to instabilities at the interfaces. Hence, films were synthesized on bare copper foils by controlling the oxygen partial pressure during sintering. Using these techniques BaTiO3 thin films with capacitances of 400 1000 nF/cm2 and breakdown voltages of 6 15 V were demonstrated. The films synthesized via either techniques exhibited stable dielectric properties up to 8 GHz owing to fine grain sizes.

With the enormously developing of the wireless communication technology, the electromagnetic environment exposing to the electrical devices is becoming more and more complex. Besides, the trends of designing high-speed digital computer systems are toward fast edge rates, high clock frequencies, and low voltage levels. The electromagnetic susceptibility (EMS) or immunity of the high-speed circuit has become an important issue today apparently. In this thesis, we will firstly establish the measurement environment and calibration technology for numerical validation. Then we employ the three-dimension finite-differential time-domain (3D-FDTD) numerical method compared to the finite element method (FEM) to simulate the EMS behavior of the power delivery network (PDN) and traces of the printed circuit boards (PCB). In addition to several types of layout of the traces studied in this thesis, we also explain the mechanism and phenomenon of the EMS of the power/ground planes of the PCB. Besides the EMS behavior research of the traditional solutions to suppress the power noise, we propose an electromagnetic bandgap structure (EBG) which has the broadband suppression of the power noise and is validated to be effective to improve the EMS problems. Finally, we also propose a novel concept to increase the signal integrity (SI) by shielding design.

In this dissertation, a new signaling scheme known as Constant Voltage Power Transmission Line (CV-PTL) is presented to supply power to a digital I/O circuit. This signaling scheme provides power through a transmission line in place of a power plane while dynamically changing the impedance of the power delivery network to keep a constant voltage at the power pin of the IC. Consequently, this reduces the effects of return path discontinuities and can improve the quality of output signal by reducing power and ground bounce. Through theory, simulation, and measurements, we show that this new method can be used to reduce jitter and eye height with the proposed PDN methodology. In addition, the signaling scheme was extended to vertically-stacked 3D integrated circuits (3D ICs). It is known that power supply noise worsens as one goes higher up in the stack of dies due to increased interconnect inductance. However, by utilizing the CV-PTL concept in the PDN design of a 3-layer 3DIC system, the circuit showed considerable improvement in power supply noise and peak-to-peak jitter as compared to the conventional design approach. In addition to signal and power integrity of these signaling schemes, the noise coupling between digital and RF components is also investigated. A simple design for mitigating the coupling of power supply noise in mixed-signal electronics is presented. Currently used methods, such as electromagnetic bandgap structures have been shown to exhibit excellent noise isolation characteristics, and are a popular area of research in this area. However, these structures can pose difficulties for signal integrity. The proposed method extends the previous power transmission line work to address both the power supply noise generation and isolation. Test vehicles using these proposed methods, as well as using an EBG structure were fabricated and tested with regards to power supply noise, jitter, and noise isolation. The proposed methods show significant improvements in almost all performance metrics as compared to EBG. Finally, this dissertation discusses the effect of implementing a power transmission line in a power distribution network composed of a switching regulator and a voltage regulator module. The DC conductor losses of the PTL can not only affect power efficiency of the entire system, but can also affect the proper operation of the linear regulator module when supporting large currents. Consequently, recommendations are made on the design of the PTL to ensure proper operation and efficiency.

The Internet of Things (IoT) has ushered in an age where low-power sensors generate data which are communicated to a back-end cloud for massive data computation tasks. From the hardware perspective this implies co-existence of several power-efficient sub-systems working harmoniously at the sensor nodes capable of communication and high-speed processors in the cloud back-end. The package-board system-level design plays a crucial role in determining the performance of such low-power sensors and high-speed computing and communication systems. Although there exist several commercial solutions for electromagnetic and circuit analysis and verification, problem diagnosis and design tools are lacking leading to longer design cycles and non-optimal system designs. This work aims at developing methodologies for faster analysis, sensitivity based diagnosis and multi-objective design towards signal integrity and power integrity of such package-board system layouts. The first part of this work aims at developing a methodology to enable faster and more exhaustive design space analysis. Electromagnetic analysis of packages and boards can be performed in time domain, resulting in metrics like eye-height/width and in frequency domain resulting in metrics like s-parameters and z-parameters. The generation of eye-height/width at higher bit error rates require longer bit sequences in time domain circuit simulation, which is compute-time intensive. This work explores learning based modelling techniques that rapidly map relevant frequency domain metrics like differential insertion-loss and cross-talk, to eye-height/width therefore facilitating a full-factorial design space sweep. Numerical results performed with artificial neural network as well as least square support vector machine on SATA 3.0 and PCIe Gen 3 interfaces generate less than 2% average error with order of magnitude speed-up in eye-height/width computation. Accurate power distribution network design is crucial for low-power sensors as well as a cloud sever boards that require multiple power level supplies. Achieving target power-ground noise levels for low power complex power distribution networks require several design and analysis cycles. Although various classes of analysis tools, 2.5D and 3D, are commercially available, the presence of design tools is limited. In the second part of the thesis, a frequency domain mesh-based sensitivity formulation for DC and AC impedance (z-parameters) is proposed. This formulation enables diagnosis of layout for maximum impact in achieving target specifications. This sensitivity information is also used for linear approximation of impedance profile updates for small mesh variations, enabling faster analysis. To enable designing of power delivery networks for achieving target impedance, a mesh-based decoupling capacitor sensitivity formulation is presented. Such an analytical gradient is used in gradient based optimization techniques to achieve an optimal set of decoupling capacitors with appropriate values and placement information in package/boards, for a given target impedance profile. Gradient based techniques are far less expensive than the state of the art evolutionary optimization techniques used presently for a decoupling capacitor network design. In the last part of this work, the functional similarities between package-board design and radio frequency imaging are explored. Qualitative inverse-solution methods common to the radio frequency imaging community, like Tikhonov regularization and Landweber methods are applied to solve multi-objective, multi-variable signal integrity package design problems. Consequently a novel Hierarchical Search Linear Back Projection algorithm is developed for an efficient solution in the design space using piecewise linear approximations. The presented algorithm is demonstrated to converge to the desired signal integrity specifications with minimum full wave 3D solve iterations.

Three-dimensional (3-D) system integration is believed to be a promising technology and has gained tremendous momentum in the semiconductor industry recently. The Silicon interposer is the key enabler for the 3-D systems, and is expected to have high input/output counts, fine wiring lines and many TSVs. Modeling and design of the silicon interposer can be challenging and is becoming a critical task. This dissertation mainly focuses on developing an efficient modeling approach for silicon interposers in 3-D systems. The developed numerical methods can be classified as several categories. 1. The investigation of the coupling effects in large TSV arrays in silicon interposers. The importance of coupling between TSVs for low resistivity silicon substrates is quantified both in frequency and time domains. This has been compared with high resistivity silicon substrates. 2. The development of an electromagnetic modeling approach for non-uniform TSVs. To model the complex TSV structures, an approach for modeling conical TSVs is proposed first. Later a hybrid modeling method which combines the conical TSV modeling method and cylindrical modeling method is proposed to model the non-uniform TSV structures. 3. The development of a hybrid modeling approach for power delivery networks (PDN) with through-silicon vias (TSVs). The proposed approach extends multi-layer finite difference method (M-FDM) to include TSVs by extracting their parasitic behavior using an integral equation based solver. 4. The development of an efficient approach for modeling signal paths with TSVs in silicon interposers. The proposed method utilizes the 3-D finite-difference frequency-domain (FDFD) method to model the redistribution layer (RDL) transmission lines. A new formulation on incorporating multiport networks into the 3-D FDFD formulation is presented to include the parasitic effects of TSV arrays in the system matrix. 5. The development of a 3-D FDFD non-conformal domain decomposition method. The proposed method allows modeling individual domains independently using the FDFD method with non-matching meshing grids at interfaces. This non-conformal domain decomposition method is applied to model interconnections in silicon interposer.

Les contraintes économiques actuelles amènent les entreprises d'électronique non seulement à innover à un rythme très soutenu mais aussi à réduire le cycle de conception des nouveaux produits. Afin de rester compétitives, ces entreprises doivent proposer régulièrement de nouveaux produits comportant de nouvelles fonctionnalités, ou améliorant les performances des produits de la génération précédente. Les progrès réalisés peuvent être quantifiés par exemple en terme de vitesse de fonctionnement, encombrement, autonomie et consommation d'énergie. La conception des cartes électroniques incluant ces contraintes est alors délicate. En effet, l'intégration de nouvelles fonctions tout comme la miniaturisation des produits entraînent une densification du circuit imprimé. Le nombre de couches utilisé augmente, l'isolement entre les signaux diminue, l'utilisation de circuits intégrés comportant différentes fonctions comme les SOC ou les SIP entraîne une multiplication du nombre de potentiels d'alimentation. L'augmentation des performances des systèmes impliquent une élévation du taux de débits de données circulant au sein du circuit imprimé et par conséquent l'augmentation des fréquences d'horloge et des signaux. Ces contraintes entraînent l'apparition de problèmes de compatibilité électromagnétique, d'intégrité du signal et d'intégrité de puissance. Il est alors nécessaire de limiter les risques de dysfonctionnement de la carte par une maîtrise des phénomènes qui se produisent d'une part par une analyse de dimensionnement précise afin d'éliminer ou de réduire les problèmes au plus tôt dans la phase de conception et d'autre part en effectuant des simulations de validation une fois la carte terminée. Cette thèse proposée par la société Thales Communications and Security en collaboration avec le laboratoire des Systèmes et Applications des Technologies de l'Information et de l’Énergie (SATIE) de l’École Normale Supérieure de Cachan dans le cadre d'une Convention Industrielle de Formation par la REcherche (CIFRE) a pour but le développement d'une méthodologie d'analyse et de conception du réseau du distribution d'énergie de cartes numériques complexes dans le but de garantir leur fonctionnement sans, ou en réduisant le nombre d'itérations de prototypage. L'introduction au contexte, une description du système étudié et des phénomènes physiques régissant son fonctionnement ainsi qu'un état de l'art des techniques d'analyse d'intégrité de puissance constituent le premier chapitre de ce mémoire. La présentation du véhicule de test, support de tous les résultats de mesure, conçu durant la deuxième année de thèse est l'objet du second chapitre. Ce chapitre dénombre et décrit l'ensemble des scenarii et des réalisations créés pour la mesure des phénomènes propres à l'intégrité de puissance et la corrélation de résultats de simulation avec ceux obtenus en mesure. Dans une troisième partie, les techniques de modélisations de chaque élément constituant le réseau de distribution d'énergie sont décrites. Afin de démontrer la validité des modèles utilisés, les résultats de simulation obtenus pour chaque élément ont été confrontés à des résultats de mesure. Le quatrième chapitre présente la méthodologie de conception et d'analyse de la stabilité des alimentations développée suite aux résultats obtenus des différentes techniques de modélisation. Les outils utilisés sont précisément décrits et les résultats de simulation confrontés à ceux de mesure du système complet du véhicule de test. Dans le chapitre 5, l'intérêt de la modélisation des réseaux de distribution d'énergie sera étendu aux études d'intégrité du signal en démontrant comment son inclusion aux simulations permet d'obtenir, lors de la mise en œuvre de co-simulations, des résultats de simulation plus proches de la réalité. Enfin, la dernière partie de ce document synthétise les travaux de la thèse, porte un regard critique et propose quelques perspectives de travaux futurs. / Today's economical context leads electronics and high-tech corporations not only to innovate with a sustained rhythm but also to reduce the design cycle of new products. In order to remain competitive, these corporations must release regularly new products with new functionalities or enhancing performances of the last generation of this product. The enhancement from one generation of the product to the other can be quantified by the speed of execution of a task, the package size or form factor, the battery life and power consumption.The design methodology following these constraints is thus very tough. Indeed, integration of new functionalities as miniaturization of products imply a densification of the printed circuit board. The number of layer in the stack up is increased, isolation between nets is reduced, the use of integrated circuits embedding different functions as SOC or SIP implies a multiplication of the number of voltages. Moreover the increase of circuit performances implies a increasing data rate exchanged between component of the same printed circuit board and occasioning a widening of the reference clock and signal frequency spectrum. These design constraints are the root cause of the apparition of electromagnetic compatibility, signal integrity and power integrity issues. Failure risks must then be limited by fully understanding phenomenon occurring on the board by, on one side, realizing a precise dimensioning pre layout analysis aiming the elimination or reduction of the issues at the beginning of the design cycle, and on the other side, validating the layout by post layout simulation once the printed circuit board routed.This study proposed by Thales Communication and Security in collaboration with public research laboratory SATIE (System and Application of Energy and Information Technologies) of Ecole Normale Supérieure de Cachan within a industrial convention for development through research aims to develop a design methodology for power delivery network of digital printed circuit board with the goal of ensuring good behavior without or by reducing the number of prototypes.The first chapter of this manuscript include an introduction to the context of the study, a precise description of the studied system and the physical phenomenon ruling its behavior, and finally a state of the art of the power integrity technique analysis. A presentation of the test vehicle, designed during the work and support of all measurement results will constitute the focus of second chapter. This chapter presents and describes all the scenarios and implementations created for the observation and measurement of Power Integrity phenomenon and realise measurement-simulation results correlation. In a third part, modeling techniques of each element of the Power Delivery Network are described. The validity of the models is proven by correlating simulation results of each element with measurement results. The fourth chapter presents the analysis and design methodology developed from the results of the different modeling techniques presented in the previous chapter. Simulation tools and their configuration are precisely described and simulation results are compared with measurement results obtained on the test vehicle for the whole system. In the fifth chapter, the interest of power delivery network model will be extended to signal integrity analysis demonstrating how including this model allows to obtain simulation results closer from measurement results by running Signal Integrity Power aware simulation. Finally, the last part of this document synthetizes the work realized and presented in this document, takes a critical look on it and proposes future works and orientations to extend knowledges and understanding of Power Integrity Phenomenon.