In high-speed digital circuits, in order to utilize the space of printed circuit boards efficiently, the signal via is a heavily used interconnection structure to communicate different signal layers. However, the interconnection discontinuities will result in the degradation of the signal integrity and become a crucial issue for IC designers. To analyze the problems accurately and fast using the hybrid physical equivalent model which combining the transmission line model, slot model, via model, and decoupling capacitor model, etc. Based on the method, we can get a good result of simulation and compute faster than Ansoft HFSS. In addition, by the hybrid physical model method, we simulate and discuss several interesting issues such as resonance in power/ground planes, and the effect of the simultaneous switching noise, we also improve the bad effect of the printed circuit boards existing vias by some ways.

In this dissertation, a new signaling scheme known as Constant Voltage Power Transmission Line (CV-PTL) is presented to supply power to a digital I/O circuit. This signaling scheme provides power through a transmission line in place of a power plane while dynamically changing the impedance of the power delivery network to keep a constant voltage at the power pin of the IC. Consequently, this reduces the effects of return path discontinuities and can improve the quality of output signal by reducing power and ground bounce. Through theory, simulation, and measurements, we show that this new method can be used to reduce jitter and eye height with the proposed PDN methodology. In addition, the signaling scheme was extended to vertically-stacked 3D integrated circuits (3D ICs). It is known that power supply noise worsens as one goes higher up in the stack of dies due to increased interconnect inductance. However, by utilizing the CV-PTL concept in the PDN design of a 3-layer 3DIC system, the circuit showed considerable improvement in power supply noise and peak-to-peak jitter as compared to the conventional design approach. In addition to signal and power integrity of these signaling schemes, the noise coupling between digital and RF components is also investigated. A simple design for mitigating the coupling of power supply noise in mixed-signal electronics is presented. Currently used methods, such as electromagnetic bandgap structures have been shown to exhibit excellent noise isolation characteristics, and are a popular area of research in this area. However, these structures can pose difficulties for signal integrity. The proposed method extends the previous power transmission line work to address both the power supply noise generation and isolation. Test vehicles using these proposed methods, as well as using an EBG structure were fabricated and tested with regards to power supply noise, jitter, and noise isolation. The proposed methods show significant improvements in almost all performance metrics as compared to EBG. Finally, this dissertation discusses the effect of implementing a power transmission line in a power distribution network composed of a switching regulator and a voltage regulator module. The DC conductor losses of the PTL can not only affect power efficiency of the entire system, but can also affect the proper operation of the linear regulator module when supporting large currents. Consequently, recommendations are made on the design of the PTL to ensure proper operation and efficiency.

This research focuses on the development of engineered materials, also known as meta- materials, with desirable effective constitutive parameters: electric permittivity (epsilon) and magnetic permeability (mu) to decouple antennas and noise mitigation from electromagnetic systems. An interesting phenomenon of strong relevance to a wide range of problems, where electromagnetic interference is of concern, is the elimination of propagation when one of the constitutive parameters is negative. In such a scenario, transmission of electromagnetic energy would cease, and hence the coupling between radiating systems is reduced. In the first part of this dissertation, novel electromagnetic artificial media have been developed to alleviate the problem of mutual coupling between high-profile and ow-profile antenna systems. The developed design configurations are numerically simulated, and experimentally validated. In the mutual coupling problem between high-profile antennas, a decoupling layer based on artificial magnetic materials (AMM) has been developed and placed between highly-coupled monopole antenna elements spaced by less than Lambda/6, where Lambda is the operating wavelength of the radiating elements. The decoupling layer not only provides high mutual coupling suppression (more than 20-dB) but also maintains good impedance matching and low correlation between the antenna elements suitable for use in Multiple-Input Multiple-Output (MIMO) communication systems. In the mutual coupling problem between low-profile antennas, novel sub-wavelength complementary split-ring resonators (CSRRs) are developed to decouple microstrip patch antenna elements. The proposed design con figuration has the advantage of low-cost production and maintaining the pro file of the antenna system unchanged without the need for extra layers. Using the designed structure, a 10-dB reduction in the mutual coupling between two patch antennas has been achieved. The second part of this dissertation utilizes electromagnetic artificial media for noise mitigation and reduction of undesirable electromagnetic radiation from high-speed printed-circuit boards (PCBs) and modern electronic enclosures with openings (apertures). Numerical results based on the developed design configurations are presented, discussed, and compared with measurements. To alleviate the problem of simultaneous switching noise (SSN) in high-speed microprocessors and personal computers, a novel technique based on cascaded CSRRs has been proposed. The proposed design has achieved a wideband suppression of SSN and maintained a robust signal integrity performance. A novel use of electromagnetic bandgap (EBG) structures has been proposed to mitigate undesirable electromagnetic radiation from enclosures with openings. By using ribbon of EBG surfaces, a significant suppression of electromagnetic radiation from openings has been achieved.

Design metrics such as area, timing and power are generally considered as the primary criteria in the design of modern day circuits, however, the minimization of power supply noise, among other noise sources, is appreciably more important since not only can it cause a degradation in these parameters but can cause entire chips to fail. Ensuring the integrity of the power supply voltage in the power distribution network of a chip is therefore crucial to both building reliable circuits as well as preventing circuit performance degradation. Power supply noise concerns, predicted over two decades ago, continue to draw significant attention, and with present CMOS technology projected to keep on scaling, it is shown in this work that these issues are not expected to diminish. This research also considers the management and on-chip detection of power supply noise. There are various methods of managing power supply noise, with the use of decoupling capacitors being the most common technique for suppressing the noise. An in-depth analysis of decap structures including scaling effects is presented in this work with corroborating silicon results. The applicability of various decaps for given design constraints is provided. It is shown that MOS-metal hybrid structures can provide a significant increase in capacitance per unit area compared to traditional structures and will continue to be an important structure as technology continues to scale. Noise suppression by means of current shifting within the clock period of an ALU block is further shown to be an additional method of reducing the minimum voltage observed on its associated supply. A simple, and area and power efficient technique for on-chip supply noise detection is also proposed.

The main objective of this thesis is to develop models for the power distribution network of high performance gigascale chips. The two main concerns in distributing power in a chip are voltage drop and electromigration-induced reliability failures. The voltage drop on the power distribution network is due to IR-drop and simultaneous switching noise. IR-drop is the voltage drop due to current passing through the resistances of the power distribution network. Simultaneous switching noise is due to varying current passing through the inductances of the power distribution network. Compact physical models are derived for the IR-drop and electromigration for different types of packages. These chip-package co-design models enable designers in the early stages of the design to estimate the on-chip interconnect resources, and also to choose type and size of the package required for power distribution. Modeling of the simultaneous switching noise requires the simulation of a large circuit with thousands of inductances. The main obstacle challenging the simulation of a simultaneous switching noise circuit model is the computing resources required to solve the dense inductance matrix. In this work, a new relative inductance matrix is introduced to solve massively coupled RLC interconnects. It is proven that the analysis using this method is accurate for a wide frequency range and all configurations. Using the new inductance matrix makes the circuit simulations significantly faster without losing accuracy.

This research focuses on the development of engineered materials, also known as meta- materials, with desirable effective constitutive parameters: electric permittivity (epsilon) and magnetic permeability (mu) to decouple antennas and noise mitigation from electromagnetic systems. An interesting phenomenon of strong relevance to a wide range of problems, where electromagnetic interference is of concern, is the elimination of propagation when one of the constitutive parameters is negative. In such a scenario, transmission of electromagnetic energy would cease, and hence the coupling between radiating systems is reduced. In the first part of this dissertation, novel electromagnetic artificial media have been developed to alleviate the problem of mutual coupling between high-profile and ow-profile antenna systems. The developed design configurations are numerically simulated, and experimentally validated. In the mutual coupling problem between high-profile antennas, a decoupling layer based on artificial magnetic materials (AMM) has been developed and placed between highly-coupled monopole antenna elements spaced by less than Lambda/6, where Lambda is the operating wavelength of the radiating elements. The decoupling layer not only provides high mutual coupling suppression (more than 20-dB) but also maintains good impedance matching and low correlation between the antenna elements suitable for use in Multiple-Input Multiple-Output (MIMO) communication systems. In the mutual coupling problem between low-profile antennas, novel sub-wavelength complementary split-ring resonators (CSRRs) are developed to decouple microstrip patch antenna elements. The proposed design con figuration has the advantage of low-cost production and maintaining the pro file of the antenna system unchanged without the need for extra layers. Using the designed structure, a 10-dB reduction in the mutual coupling between two patch antennas has been achieved. The second part of this dissertation utilizes electromagnetic artificial media for noise mitigation and reduction of undesirable electromagnetic radiation from high-speed printed-circuit boards (PCBs) and modern electronic enclosures with openings (apertures). Numerical results based on the developed design configurations are presented, discussed, and compared with measurements. To alleviate the problem of simultaneous switching noise (SSN) in high-speed microprocessors and personal computers, a novel technique based on cascaded CSRRs has been proposed. The proposed design has achieved a wideband suppression of SSN and maintained a robust signal integrity performance. A novel use of electromagnetic bandgap (EBG) structures has been proposed to mitigate undesirable electromagnetic radiation from enclosures with openings. By using ribbon of EBG surfaces, a significant suppression of electromagnetic radiation from openings has been achieved.

Design metrics such as area, timing and power are generally considered as the primary criteria in the design of modern day circuits, however, the minimization of power supply noise, among other noise sources, is appreciably more important since not only can it cause a degradation in these parameters but can cause entire chips to fail. Ensuring the integrity of the power supply voltage in the power distribution network of a chip is therefore crucial to both building reliable circuits as well as preventing circuit performance degradation. Power supply noise concerns, predicted over two decades ago, continue to draw significant attention, and with present CMOS technology projected to keep on scaling, it is shown in this work that these issues are not expected to diminish. This research also considers the management and on-chip detection of power supply noise. There are various methods of managing power supply noise, with the use of decoupling capacitors being the most common technique for suppressing the noise. An in-depth analysis of decap structures including scaling effects is presented in this work with corroborating silicon results. The applicability of various decaps for given design constraints is provided. It is shown that MOS-metal hybrid structures can provide a significant increase in capacitance per unit area compared to traditional structures and will continue to be an important structure as technology continues to scale. Noise suppression by means of current shifting within the clock period of an ALU block is further shown to be an additional method of reducing the minimum voltage observed on its associated supply. A simple, and area and power efficient technique for on-chip supply noise detection is also proposed.

<p>Microelectronics is heading towards larger and larger systems implemented on a single chip. In wireless communication equipment, e.g., cellular phones, handheld computers etc., both analog and digital circuits are required. If several integrated circuits (ICs) are used in a system, a large amount of the power is consumed by the communication between the ICs. Furthermore, the communication between ICs is slow compared with on-chip communication. Therefore, it is favorable to integrate the whole system on a single chip, which is the objective in the system-on-chip (SoC) approach.</p><p>In a mixed-signal SoC, analog and digital circuits share the same chip. When digital circuits are switching, they produce noise that is spread through the silicon substrate to other circuits. This noise is known as substrate noise. The performance of sensitive analog circuits is degraded by the substrate noise in terms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamic range. Another problem is the design of the clock distribution net, which is challenging in terms of obtaining low power consumption, sharp clock edges, and low simultaneous switching noise.</p><p>In this thesis, a noise reduction strategy that focus on reducing the amount of noise produced in digital clock buffers, is presented. The strategy is to use a clock with long rise and fall times. It is also used to relax the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip show that the strategy can be implemented in an IC with low cost in terms of speed and power consumption. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective here is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling when no guard band is used, up to a certain frequency that is highly dependent of the chip structure. When a guard band is introduced in one of the analyzed test structures, the bulk resulted in much higher attenuation compared with SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has also been designed in a 0.13 µ SOI process.</p> / Report code: LiU-Tek-Lic-2005:33.

In many consumer products, e.g., cellular phones and handheld computers, both digital and analog circuits are required. Nowadays, it is possible to implement a large subsystem or even a complete system, that earlier required several chips, on a single chip. A system on chip (SoC) has generally the advantages of lower power consumption and a smaller fabrication cost compared with multi-chip solutions. The switching of digital circuits generates noise that is injected into the silicon substrate. This noise is known as substrate noise and is spread through the substrate to other circuits. The substrate noise received in an analog circuit degrades the performance of the circuit. This is a major design issue in mixed-signal ICs where analog and digital circuits share the same substrate. Two new noise reduction methods are proposed in this thesis work. The first focuses n reducing the switching noise generated in digital clock buffers. The strategy is to use a clock with long rise and fall times in conjunction with a special D flip-flop. It relaxes the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip implemented in a 0.35 μm CMOS technology show that the method can be implemented in an IC with low cost in terms of speed and power consumption. A noise reduction up to 50% is obtained by using the method. The measured power consumption of the digital circuit, excluding the clock buffer, increased 14% when the rise and fall times of the clock were increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns corresponding to an increase of 50% in propagation delay of the registers. The second noise reduction method focuses on reducing simultaneous switching noise below half the clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as close to periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. For this purpose we use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 μm CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB using the proposed method. The cost is mainly an increase in power consumption of almost a factor of three. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling if no guard band is used, up to a certain frequency that is dependent of the test case. Introducing a guard band resulted in a higher attenuation of substrate noise in bulk than in SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has been designed in a 0.13 μm SOI CMOS technology. The measuring circuit uses a single comparator per channel where several passes are used to capture the waveform. Measurements on a fabricated testchip indicate that the measuring circuit works as intended. A small part of this thesis work has been done in the area of digit representation in digital circuits. A new approach to convert a number from two’s complement representation to a minimum signed-digit representation is proposed. Previous algorithms are working either from the LSB to the MSB (right-to-left) or from the MSB to the LSB (left-to-right). The novelty in the proposed algorithm is that the conversion is done from left-to-right and right-to-left concurrently. Using the proposed algorithm, the critical path in a conversion circuit can be nearly halved compared with the previous algorithms. The area and power consumption, of the implementation of the proposed algorithm, are somewhere between the left-to-right and right-to-left implementations. / Articles I, II, III, IV, VII and IX are published with permisson from IEEE dated 07/05/18. Copyright IEEE.

In modern high-speed digital circuits, the space of the traditional single-layered or double-layered circuit board is not enough, therefore multi-layered circuit and stacked distribution technology are widely applied to many applications. The signal via is a vertical interconnection structure to communicate different signal layers, which will be seriously interfere with the simultaneous switching noise by via through the parallel plate cavity that consists of power and ground plane. It is an important issue to minimize the influence from noise. In multi-layered printed circuit boards, shorting vias are usually utilized to interconnect the planes with the same voltage level. The major theme of this thesis is the placement of shorting vias affecting plane cavity mode. And we propose a design rule of the shorting vias to significantly decrease the simultaneous switching noise and improve the power integrity of multi-layered circuit board.