In conventional design of power delivery networks (PDNs), the PDN impedance is required to be less than the target impedance over the frequency range of interest to minimize the IR drop and to suppress the inductive noise during data transitions. As a result, most PDNs in high-speed systems consist of power and ground planes to provide a low-impedance path between the voltage regulator module (VRM) and the integrated circuit (IC) on the printed circuit board (PCB). For off-chip signaling, charging and discharging signal transmission lines induce return currents on the power and ground planes. The return current always follows the path of least impedance on the reference plane closest to the signal transmission line. The return current path plays a critical role in maintaining the signal integrity of the bits propagating on the signal transmission lines. The problem is that the disruption between the power and ground planes induces return path discontinuities (RPDs), which create displacement current sources between the power and ground planes. The current sources excite the plane cavity and cause voltage fluctuations. These fluctuations are proportional to the plane impedance since the current is drawn through the PDN by the driver. Therefore, low PDN impedance is required for power supply noise reduction. Alternatively, methods of preventing RPDs can be used to suppress power supply noise. Using a power transmission line (PTL) eliminates the discontinuity between the power and ground planes, thereby preventing the RPD effects. In this approach, transmission lines replace the power plane for conveying power from the VRM to each IC on the PCB. The PTL-based PDN enables both power and signal transmission lines to be referenced to the same ground plane so that a continuous current path can be formed, unlike the power-plane-based PDN. As a result, a closed current loop is achieved, and the voltage fluctuation caused by RPDs is removed in idealistic situations. Without the RPD-related voltage fluctuation, reducing the PDN impedance is not as critical as in the power-plane-based approach. Instead, the impedance of the PTL is determined by the impedance of the signaling circuits. To use the PTL-based PDN in a practical signaling environment, several issues need to be solved. First, the dc drop coming from the source termination of the PTL needs to be addressed. The driver being turned on and off dictates the current flow through the PTL, causing the dc drop to be dynamic, which depends on the data pattern. Second, impedance mismatch between the PTL and termination can occur due to manufacturing variations. Third, an increase in the number of PCB traces should be addressed by devising a method to feed more than one driver with one PTL. Lastly, the power required to transmit 1 bit of data should be optimized for the PTL by using a new signaling scheme and adjusting the impedance of the signaling circuit. Constant flow of current through the PDN is one solution proposed to address the first two issues. Constant current removes the dynamic characteristics of the dc drop by inducing a fixed amount of dc drop over the PTL. Moreover, constant current keeps the PTL fully charged at all times, and thereby eliminates the process of repeatedly charging and discharging the power transmission line. The constant current PTL (CCPTL) scheme maintains constant current flow regardless of the input data pattern. Early results on the CCPTL scheme have been discussed along with the measurements. The CCPTL scheme severs the link between the current flowing through the PTL and the output data of the I/O driver connected to it. Also, it eliminates the charging and discharging process of the PTL, thereby completely eliminating power supply noise in idealistic situations. To reduce any associated power penalty, a pseudo-balanced PTL (PBPTL) scheme is also proposed using the PTL concept. A pseudo-balanced (PB) signaling scheme, which uses an encoding technique to map N-bit data onto M-bit encoded data with fixed number of 1s and 0s, is applied. When the PB signaling scheme is combined with the PTL, the jitter performance improves significantly as compared to currently practiced design approach.

The switching noise in a hard-switched point-of-load (POL) converter may result in false turn on, electromagnetic interference issues, or even device breakdown. A resonant cross-commutated buck (rccBuck) converter operates with low noise since all MOSFETs are turned on with zero voltage within a wide load range. A state-space model was developed to calculate the voltage gain, voltage stresses, and current stresses. Design guidelines for the rccBuck converter operating at continuous voltage mode or discontinuous voltage mode are provided. The design methodology of a one-turn inductor with significant ac and dc fluxes is given. Four fabricated one-turn inductors achieved 2.1% higher efficiency and 50% smaller total magnetic volume than the commercial inductors in the same rccBuck converter. The Omni-coupled inductors (OCI), composed of a twisted E-E core and PCB windings, further improve power density and efficiency. The core loss and inductances were modeled from a complex reluctance network. According to the loss-volume Pareto fronts, the total inductor loss was minimized within a smaller volume than that of discrete inductors. The expectations were validated by an OCI-based rccBuck converter switched at 2 MHz with 12 V input, 3.3 V at 20 A output, and peak efficiency of 96.2%. The small-signal model with a good accuracy up to half switching frequency was developed based on the averaged equivalent circuit. The transient performance of an rccBuck regulator is comparable to that of a second-order buck regulator with the same switching frequency, output capacitance, and closed-loop bandwidth. / Ph. D. / The switching noise in a hard-switched point-of-load (POL) converter may result in false turn on, electromagnetic interference issues, or even device breakdown. A resonant cross-commutated buck (rccBuck) converter operates with low noise since all MOSFETs are turned on with zero voltage within a wide load range. A state-space model was developed to calculate the voltage gain, voltage stresses, and current stresses. Design guidelines for the rccBuck converter operating at continuous voltage mode or discontinuous voltage mode are provided. The design methodology of a one-turn inductor with significant ac and dc fluxes is given. Four fabricated one-turn inductors achieved 2.1% higher efficiency and 50% smaller total magnetic volume than the commercial inductors in the same rccBuck converter. The Omni-coupled inductors (OCI), composed of a twisted E-E core and PCB windings, further improve power density and efficiency. The core loss and inductances were modeled from a complex reluctance network. According to the loss-volume Pareto fronts, the total inductor loss was minimized within a smaller volume than that of discrete inductors. The expectations were validated by an OCI-based rccBuck converter switched at 2 MHz with 12 V input, 3.3 V at 20 A output, and peak efficiency of 96.2%. The small-signal model with a good accuracy up to half switching frequency was developed based on the averaged equivalent circuit. The transient performance of an rccBuck regulator is comparable to that of a second-order buck regulator with the same switching frequency, output capacitance, and closed-loop bandwidth.

This thesis focuses on the modeling and solutions of the simultaneous switching noise (SSN) problems in the power delivery networks (PDN) of high-speed digital circuit packages. An efficient numerical approach based on two-dimension (2D) finite-difference time-domain (FDTD) method combined with the lumped circuit model of the interconnection is proposed to model the PDN of a package and PCB. Based on this approach, the mechanism of noise coupling between package and PCB can be analyzed. In addition, a novel photonic crystal power layer (PCPL) design for the PDN of the package or PCB is proposed to suppress the SSN. The periodic High-Dk material is embedded into the substrate layer between the power and ground planes. Both modeling and measurement demonstrate the PCPL can form a wide stopband well with excellent suppression of the SSN propagation in the substrate and the corresponding electromagnetic interference (EMI).

The objective of this dissertation is to develop electrical modeling and co-simulation methodologies for signal and power integrity of package and board applications. The dissertation includes 1) the application of the finite element method to the optimization for decoupling capacitor selection and placement on a power delivery network (PDN), 2) the development of a PDN modeling method effective for multidimensional and multilayer geometries, 3) the analysis and modeling of return path discontinuities (RPDs), and 4) the implementation of the absorbing boundary condition for PDN modeling. The optimization technique for selection and placement of decoupling capacitors uses a genetic algorithm (GA) and the multilayer finite element method (MFEM), a PDN modeling method using FEM. The GA is customized for the decoupling problem to enhance the convergence speed of the optimization. The mathematical modifications necessary for the incorporation of the capacitor model into MFEM is also presented. The main contribution of this dissertation is the development of a new modeling method, the multilayer triangular element method (MTEM), for power/ground planes of a PDN. MTEM creates a surface mesh on each plane-pair using dual graphs; a non-uniform triangular mesh (Delaunay triangulation) and its orthogonal counterpart (Voronoi diagram), to which electromagnetic and equivalent circuit concepts are applied. The non-uniform triangulation is especially efficient for discretizing multidimensional and irregular geometries which are common in package and board PDNs. Moreover, MTEM generates a sparse, banded, and symmetric system matrix, which enables efficient computations. For a given plane-pair, MTEM extracts an equivalent circuit that is consistent with the physics-based planar-circuit model of a plane-pair. Thus, the values of the lumped elements can be simply calculated from the physical parameters, such as material properties and mesh geometries of each unit-cell. Consequently, the modeling of MTEM is flexible and easy to modify for further extensions, such as the incorporation of external circuits, e.g. decoupling capacitors and vertical interconnects. Power and ground planes provide paths for the return current of signal traces. Typically, planes have discontinuities such as via holes, plane cutouts, and split planes that disturb flow of signal return currents. At the discontinuity, return currents have to detour or switch to different layers, causing signal and power integrity problems. Therefore, a separate analysis of signal interconnects will neglect the significant coupling with a PDN, and the result will not be reliable. In this dissertation, the co-simulation of the signal and power integrity is presented focusing on the modeling of RPDs created by split planes, apertures, and vias. Plane resonance is one of the main sources of power integrity problems in package and board PDNs. A number of techniques have been developed and published in literature to reduce or prevent the resonance of a plane-pair. One of the techniques is to surround plane-pair edges with absorbing material that effectively damps the outgoing parallel-plate wave and minimizes the reflection. To model this behavior, the boundary condition of MTEM needs to be changed from its original form, the open-circuit boundary condition. In this dissertation, the application of the 1st order absorbing boundary condition to MTEM is presented.

Microelectronics is heading towards larger and larger systems implemented on a single chip. In wireless communication equipment, e.g., cellular phones, handheld computers etc., both analog and digital circuits are required. If several integrated circuits (ICs) are used in a system, a large amount of the power is consumed by the communication between the ICs. Furthermore, the communication between ICs is slow compared with on-chip communication. Therefore, it is favorable to integrate the whole system on a single chip, which is the objective in the system-on-chip (SoC) approach. In a mixed-signal SoC, analog and digital circuits share the same chip. When digital circuits are switching, they produce noise that is spread through the silicon substrate to other circuits. This noise is known as substrate noise. The performance of sensitive analog circuits is degraded by the substrate noise in terms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamic range. Another problem is the design of the clock distribution net, which is challenging in terms of obtaining low power consumption, sharp clock edges, and low simultaneous switching noise. In this thesis, a noise reduction strategy that focus on reducing the amount of noise produced in digital clock buffers, is presented. The strategy is to use a clock with long rise and fall times. It is also used to relax the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip show that the strategy can be implemented in an IC with low cost in terms of speed and power consumption. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective here is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling when no guard band is used, up to a certain frequency that is highly dependent of the chip structure. When a guard band is introduced in one of the analyzed test structures, the bulk resulted in much higher attenuation compared with SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has also been designed in a 0.13 µ SOI process. / <p>Report code: LiU-Tek-Lic-2005:33.</p>

Globally Asynchronous Locally Synchronous (GALS) Design ist eine Lösung zur Skalierbarkeit und Modularität für die SoC-Integration. Heutzutage ist GALS-Design weit in der Industrie angewendet. Die meisten GALS-Systeme basieren auf Dual-Clock-FIFOs für die Kommunikation Zwischen Taktdomänen. Um Leistungsverluste aufgrund der Synchronisationslatenzzeit zu vermindern, müssen die On-Chip-FIFOs ausreichend groß sein. Dies führt jedoch oft zu erheblichen Kosten-Hardware. Effiziente GALS- Lösungen sind daher vonnöten. Diese Arbeit berichtet unsere neuesten Fortschritte in GALS Design, das auf der Pausierenden Taktung basiert. Kritische Designthemen in Bezug auf Synchronisation-szuverlässigkeit bzw. Kommunikationsfähigkeit sind systematisch und analytisch un-tersucht. Ein lose gekoppeltes GALS Data-Link-Design wird vorgeschlagen. Es unter-stützt metastabilitätsfreie Synchronisation für Sub-Takt-Baum Verzögerungen. Außer-dem unterstützt es kontinuierliche Datenübertragung für High-Throughput-Kommuni-kation. Die Rosten hinsichtlich Energie verbrauch und Chipfläche sind marginal. GALS Design ist eingesetzt, um digitales On-Chip Umschaltrauschen zu verringern. Plesiochron Taktung mit balanciertem Leistungsverbrauch zwischen GALS Blöcken wird insbesondere untersucht. Für M Taktbereiche wird eine Reduzierung um 20lgM dB für die spektralen Spitzen des Versorgungsstroms bei der Takt-Grundfrequenz theoretisch hergcleitet. Im Vergleich zu den bestehenden synchronen Lösungen, geben diese Methode eine Alternative, um das digitale schaltrauschen effektiv zu senken. Schließlich wurde die entwickelte GALS Design Methodik schon bei reale Chip-Implementierungen angewendet. Zwei komplizierte industriell relevante Test-Chips, Lighthouse und Moonrake, wurden entworfen und mit State-Of-The-Art-Technologien hergestellt. Die experimentellen Ergebnisse bzw. / Globally asynchronous locally synchronous (GALS) design presents a solution of scalability and modularity to SoC integration. Today, it has been widely applied in the industry. Most of the GALS systems are based on dual-clock FIFOs for clock domain crossing. To avoid performance loss due to synchronization latency, the on-chip FIFOs need to be sufficiently large. This, however, often leads to considerable hardware costs. Efficient design solutions of GALS are therefore in great demand. This thesis reports our latest progress in GALS design bases on pausible clocking. Critical design issues on synchronization reliability and communication performance are studied systematically and analytically. A loosely-coupled GALS data-link design is proposed. It supports metastability-free synchronization for sub-cycle clock-tree delay, and accommodates continuous data transfer for high-throughput communication. Only marginal costs of power and silicon area are required. GALS design has been employed to cope with the on-chip digital switching noise in our work. Plesiochronous clocking with power-consumption balance between GALS blocks is in particular explored. Given M clock domains, a reduction of 20lgM dB on the spectral peaks of supply current at the fundamental clock frequency is theoretically derived. In comparison with the existing synchronous design solutions, it thus presents an alternative to effective attenuation of digital switching noise. The developed GALS design methodology has been applied to chip implementation. Two complicated industry-relevant test chips, named Lighthouse and Moonrake, were designed and fabricated using state-of-the-art technologies. The experimental results as well as the on-chip measurements are reported here in detail. We expect that, our work will contribute to the practical applications of GALS design based on pausible clocking in the industry.

Mixed signal system-on-package (SoP) technology is a key enabler for increasing functional integration, especially in mobile and wireless systems. Due to the presence of multiple dissimilar modules, each having unique power supply requirements, the design of the power distribution network (PDN) becomes critical. Typically, this PDN is designed as alternating layers of power and ground planes with signal interconnects routed in between or on top of the planes. The goal for the simulation of multi-layer power/ground planes, is the following: Given a stack-up and other geometrical information, it is required to find the network parameters (S/Y/Z) between port locations. Commercial packages have extremely complicated stack-ups, and the trend to increasing integration at the package level only points to increasing complexity. It is computationally intractable to solve these problems using these existing methods. The approach proposed in this thesis for obtaining the response of the PDN is the multi-layer finite difference method (M-FDM). A surface mesh / finite difference based approach is developed, which leads to a system matrix that is sparse and banded, and can be solved efficiently. The contributions of this research are the following: 1. The development of a PDN modeler for multi-layer packages and boards called the the multi-layer finite difference method. 2. The enhancement of M-FDM using multi-port connection networks to include the effect of fringe fields and gap coupling. 3. An adaptive triangular mesh based scheme called the multi-layer finite element method (MFEM) to address the limitations of M-FDM 4. The use of modal decomposition for the co-simulation of signal nets with the PDN. 5. The use of a robust GA-based optimizer for the selection and placement of decoupling capacitors in multi-layer geometries. 6. Implementation of these methods in a tool called MSDT 1.