Abstract A range of di®erent high-quality single crystal diamonds synthesized under high pressure and high temperature (HPHT) conditions have been studied in view of their potential as candidates for specialized electronic devices with emphasis on particle detectors. The studies incorporated a long range of spectroscopic and electronic characterization techniques. Special attention was given to electronic properties and device performance re- lated to the electrical contacts applied, the type and the concentration of impur- ities and the crystallographic defects present. The electronic response of a dia- mond detector as far as impurities are concerned is predominantly determined by the single substitutional nitrogen (SSN) and boron acceptors. Di®erent tech- niques were used to assess the role of such impurities in the diamond crystals stud- ied, as well as to study the dynamics due to the interaction of such impurities with each other (compensation). Hence, the electron spin resonance (ESR) and the current-deep level transient spectroscopy (I-DLTS) techniques were used in this re- spect to extract the information concerning activation energies, nitrogen-boron dy- namics, and the nitrogen and boron concentrations. ii iii It was found that the SSN content was below 1013 cm¡3 with this result giving the approximate concentration of boron acceptors, being the same value as of that of the SSN, or slightly above. Maximum activation energies of boron acceptors were extracted from three di®erent regions in the bulk of the diamond. The values were approximately 0.311 eV § 0.0027 eV in the center region, 0.308 eV § 0.007 eV in the intermediate region and 0.29 eV § 0.007 eV at the edge region, respectively. The maximum activation energy when boron is fully compensated is about 0.37 eV. Properties of ohmic and Schottky contacts as a function of concentration of SSN and boron acceptors were investigated using Current-Voltage characteristic and photo- current measurements. Di®erent surface treatment conditions and di®erent types of diamonds (IIa, IIb and Ib) were used. Electronic properties as a function of contacts were assessed for high purity synthetic type IIa diamond detector, incorporating a time of °ight (TOF) UV laser set-up. The maximum hole collection distance at room temperature was found to be 91.00 cm, the maximum transient time for holes was about 1.00 ms and the e±ciency was approximately 41%, with contacts made of Ti/Pt/Au-Ru. When Ru-Ru contacts are applied, the maximum hole mobility and the velocity were extracted at room temperature to be about 17963.44 cm2V¡1s¡1 and 5.02 £107 cms¡1, respectively, and the e±ciency of the device is about 30%. The maximum applied external electric ¯elds with Ru-Ru contacts were increased to about 1.32 times that at low temperature and to about 1.84 times that at room temperature. iv Large signals generated by ®-particles from 228Th were obtained without using amp- li¯cation. However, a full analysis of the pulse was not possible due to the narrow bandwidth of the electronic probes used. In a detector made of type Ib diamond, with SSN concentrations of about 50 ppm, it was found that regions in the bulk exhibiting better charge collection properties contained small concentrations of uncompensated boron impurity. On the other hand, the di®erence in the concentrations of SSN between the two type Ib diamonds, with about 50 ppm and about 200 ppm of SSN concentrations, respectively, resulted in approximately 70 ps di®erence in the transit time between two detectors made of these diamonds. Keywords: Synthetic diamond, detector, HPHT, type Ib, type IIa, single substitutional ni- trogen, SSN, ESR, ARP, I-DLTS, metallization, uncompensated boron impurity, crystallographic defects, rise and decay times, charge carrier life time, charge carrier mobility, carrier mean free path , charge collection distance, carrier Schubweg.

Yes

<p>Microelectronics is heading towards larger and larger systems implemented on a single chip. In wireless communication equipment, e.g., cellular phones, handheld computers etc., both analog and digital circuits are required. If several integrated circuits (ICs) are used in a system, a large amount of the power is consumed by the communication between the ICs. Furthermore, the communication between ICs is slow compared with on-chip communication. Therefore, it is favorable to integrate the whole system on a single chip, which is the objective in the system-on-chip (SoC) approach.</p><p>In a mixed-signal SoC, analog and digital circuits share the same chip. When digital circuits are switching, they produce noise that is spread through the silicon substrate to other circuits. This noise is known as substrate noise. The performance of sensitive analog circuits is degraded by the substrate noise in terms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamic range. Another problem is the design of the clock distribution net, which is challenging in terms of obtaining low power consumption, sharp clock edges, and low simultaneous switching noise.</p><p>In this thesis, a noise reduction strategy that focus on reducing the amount of noise produced in digital clock buffers, is presented. The strategy is to use a clock with long rise and fall times. It is also used to relax the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip show that the strategy can be implemented in an IC with low cost in terms of speed and power consumption. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective here is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling when no guard band is used, up to a certain frequency that is highly dependent of the chip structure. When a guard band is introduced in one of the analyzed test structures, the bulk resulted in much higher attenuation compared with SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has also been designed in a 0.13 µ SOI process.</p> / Report code: LiU-Tek-Lic-2005:33.

In many consumer products, e.g., cellular phones and handheld computers, both digital and analog circuits are required. Nowadays, it is possible to implement a large subsystem or even a complete system, that earlier required several chips, on a single chip. A system on chip (SoC) has generally the advantages of lower power consumption and a smaller fabrication cost compared with multi-chip solutions. The switching of digital circuits generates noise that is injected into the silicon substrate. This noise is known as substrate noise and is spread through the substrate to other circuits. The substrate noise received in an analog circuit degrades the performance of the circuit. This is a major design issue in mixed-signal ICs where analog and digital circuits share the same substrate. Two new noise reduction methods are proposed in this thesis work. The first focuses n reducing the switching noise generated in digital clock buffers. The strategy is to use a clock with long rise and fall times in conjunction with a special D flip-flop. It relaxes the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip implemented in a 0.35 μm CMOS technology show that the method can be implemented in an IC with low cost in terms of speed and power consumption. A noise reduction up to 50% is obtained by using the method. The measured power consumption of the digital circuit, excluding the clock buffer, increased 14% when the rise and fall times of the clock were increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns corresponding to an increase of 50% in propagation delay of the registers. The second noise reduction method focuses on reducing simultaneous switching noise below half the clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as close to periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. For this purpose we use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 μm CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB using the proposed method. The cost is mainly an increase in power consumption of almost a factor of three. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling if no guard band is used, up to a certain frequency that is dependent of the test case. Introducing a guard band resulted in a higher attenuation of substrate noise in bulk than in SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has been designed in a 0.13 μm SOI CMOS technology. The measuring circuit uses a single comparator per channel where several passes are used to capture the waveform. Measurements on a fabricated testchip indicate that the measuring circuit works as intended. A small part of this thesis work has been done in the area of digit representation in digital circuits. A new approach to convert a number from two’s complement representation to a minimum signed-digit representation is proposed. Previous algorithms are working either from the LSB to the MSB (right-to-left) or from the MSB to the LSB (left-to-right). The novelty in the proposed algorithm is that the conversion is done from left-to-right and right-to-left concurrently. Using the proposed algorithm, the critical path in a conversion circuit can be nearly halved compared with the previous algorithms. The area and power consumption, of the implementation of the proposed algorithm, are somewhere between the left-to-right and right-to-left implementations. / Articles I, II, III, IV, VII and IX are published with permisson from IEEE dated 07/05/18. Copyright IEEE.

In February of 2014 NASA has launched the core observatory of The Global Precipitation Measurement Mission (GPM). Since then, the mission has been providing a wealth of observation data collected by the core observatory along with other satellites belonging to the mission space constellation. One of the most important data products that GPM provides is the Level 4 (L4) rainfall data product called Integrated Multi-satellitE Retrievals for GPM (IMERG). IMERG is constructed using the raw data collected by the Microwave (MW) sensors on board the constellation satellites along with the Infrared (IR) sensors on board geostationary satellites and the advance Dual-frequency Precipitation Radar (DPR) on board the GPM core satellite. The IMERG product is available globally for all interested researchers to use. In this dissertation, I focus on the applicability of IMERG in hydrologic applications, and specifically in flood peak modeling. In order to conduct a comprehensive evaluation of IMERG that is oriented towards hydrologic modeling. I have explored multiple hydrologic models which can be used to produce stream flow estimates using IMERG without the need of parameter calibration based on the model’s inputs. The calibration free capability is essential since model parameter calibration obscures the effect of the errors associated with the rainfall input on the estimated discharges, which in turn will limit our understanding about the distribution of the errors in IMERG over space and time. The two hydrologic models we used in this study are both physically based distributed models and were setup over the domain of the state of Iowa which is located in the United States’ Midwest. I also explored the performance of one of the hydrologic models’ component, which is the runoff-routing component, in order to estimate an additional portion of the errors in the discharge estimates that is not attributed to the model’s input but rather to the hydrologic model itself. A significant portion of my dissertation is concerned with identifying and using accurate methods to evaluate both IMERG and the hydrologic models’ outputs in a hydrologic context that is useful for flood modeling. Several studies have evaluated other satellite rainfall products using methods that vary in complexity. Some studies used the simplest methods of evaluation, such as, mean aerial differences and standard deviation of the differences (additive or multiplicative) compared to a benchmark rainfall product. This is done without taking the spatial dependency of the errors in space into consideration. Other studies modeled the spatial dependency (correlation) between the errors in the rainfall product, however, using Euclidean distance based approaches that do not account for the hydrologic basins’ shape and size. Nevertheless, it is important to realize that hydrologic models will eventually aggregate the rainfall values, along with the errors associated with them, through a stream network that is dichotomous in nature and does not comply with Euclidean distance. Thus, we employed a stream based evaluation framework, called the Spatial Stream Network (SSN) approaches, to characterize the errors in IMERG taking into account the stream distances and the stream connectivity information between evaluation sites. Although previously used in applications such as modeling water temperatures and pollutant transport, to the best of my knowledge this approach has not been used in rainfall product evaluation before this study. The SSN analysis of IMERG allowed me to answer the question, “What is the proper basin scale which is capable of filtering out the correlated errors in IMERG by accumulating the rainfall values through the stream network?” Finally, in order to add value to the current methods of evaluating model simulated stream flows. I proposed a time based evaluation that is capable of detecting peaks in both the observed and simulated flows and estimating the lag time of the simulated peaks. Typically, previous studies have used simple skill scores such as Root Mean Squared Errors (RMSE), correlation coefficient, and Nash-Sutcliff Efficiency (NSE) to evaluate hydrograph performance as a whole, or the difference in time to peak which involves primitive peak detection method (e.g., a moving or a defined time window). In this dissertation I propose a Continuous Wavelet Transform (CWT) based method to evaluate the peak times and shapes produced by the hydrologic model. The method is based on filtering the frequencies in the hydrograph by treating it as a signal and detecting sharp features in both the observed and time series and the phase difference between them. We also emphasized on the importance of the choice of wavelet shape used in the evaluation, and how different wavelet shapes can affect the inference about the time series.

No description available.

Microelectronics is heading towards larger and larger systems implemented on a single chip. In wireless communication equipment, e.g., cellular phones, handheld computers etc., both analog and digital circuits are required. If several integrated circuits (ICs) are used in a system, a large amount of the power is consumed by the communication between the ICs. Furthermore, the communication between ICs is slow compared with on-chip communication. Therefore, it is favorable to integrate the whole system on a single chip, which is the objective in the system-on-chip (SoC) approach. In a mixed-signal SoC, analog and digital circuits share the same chip. When digital circuits are switching, they produce noise that is spread through the silicon substrate to other circuits. This noise is known as substrate noise. The performance of sensitive analog circuits is degraded by the substrate noise in terms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamic range. Another problem is the design of the clock distribution net, which is challenging in terms of obtaining low power consumption, sharp clock edges, and low simultaneous switching noise. In this thesis, a noise reduction strategy that focus on reducing the amount of noise produced in digital clock buffers, is presented. The strategy is to use a clock with long rise and fall times. It is also used to relax the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip show that the strategy can be implemented in an IC with low cost in terms of speed and power consumption. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective here is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling when no guard band is used, up to a certain frequency that is highly dependent of the chip structure. When a guard band is introduced in one of the analyzed test structures, the bulk resulted in much higher attenuation compared with SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has also been designed in a 0.13 µ SOI process. / <p>Report code: LiU-Tek-Lic-2005:33.</p>

Mixed signal system-on-package (SoP) technology is a key enabler for increasing functional integration, especially in mobile and wireless systems. Due to the presence of multiple dissimilar modules, each having unique power supply requirements, the design of the power distribution network (PDN) becomes critical. Typically, this PDN is designed as alternating layers of power and ground planes with signal interconnects routed in between or on top of the planes. The goal for the simulation of multi-layer power/ground planes, is the following: Given a stack-up and other geometrical information, it is required to find the network parameters (S/Y/Z) between port locations. Commercial packages have extremely complicated stack-ups, and the trend to increasing integration at the package level only points to increasing complexity. It is computationally intractable to solve these problems using these existing methods. The approach proposed in this thesis for obtaining the response of the PDN is the multi-layer finite difference method (M-FDM). A surface mesh / finite difference based approach is developed, which leads to a system matrix that is sparse and banded, and can be solved efficiently. The contributions of this research are the following: 1. The development of a PDN modeler for multi-layer packages and boards called the the multi-layer finite difference method. 2. The enhancement of M-FDM using multi-port connection networks to include the effect of fringe fields and gap coupling. 3. An adaptive triangular mesh based scheme called the multi-layer finite element method (MFEM) to address the limitations of M-FDM 4. The use of modal decomposition for the co-simulation of signal nets with the PDN. 5. The use of a robust GA-based optimizer for the selection and placement of decoupling capacitors in multi-layer geometries. 6. Implementation of these methods in a tool called MSDT 1.

This thesis proposes a collaboration framework for the Web of Things based on the concepts of Service-oriented Architecture and integrated with semantic web technologies to offer new possibilities in terms of efficient asset management during operations requiring multi-actor collaboration. The motivation for the project comes from the rise in disasters where effective cross-organisation collaboration can increase the efficiency of critical information dissemination. Organisational boundaries of participants as well as their IT capability and trust issues hinders the deployment of a multi-party collaboration framework, thereby preventing timely dissemination of critical data. In order to tackle some of these issues, this thesis proposes a new collaboration framework consisting of a resource-based data model, resource-oriented access control mechanism and semantic technologies utilising the Semantic Sensor Network Ontology that can be used simultaneously by multiple actors without impacting each other’s networks and thus increase the efficiency of disaster management and relief operations. The generic design of the framework enables future extensions, thus enabling its exploitation across many application domains. The performance of the framework is evaluated in two areas: the capability of the access control mechanism to scale with increasing number of devices, and the capability of the semantic annotation process to increase in efficiency as more information is provided. The results demonstrate that the proposed framework is fit for purpose.

This thesis proposes a collaboration framework for the Web of Things based on the concepts of Service-oriented Architecture and integrated with semantic web technologies to offer new possibilities in terms of efficient asset management during operations requiring multi-actor collaboration. The motivation for the project comes from the rise in disasters where effective cross-organisation collaboration can increase the efficiency of critical information dissemination. Organisational boundaries of participants as well as their IT capability and trust issues hinders the deployment of a multi-party collaboration framework, thereby preventing timely dissemination of critical data. In order to tackle some of these issues, this thesis proposes a new collaboration framework consisting of a resource-based data model, resource-oriented access control mechanism and semantic technologies utilising the Semantic Sensor Network Ontology that can be used simultaneously by multiple actors without impacting each other’s networks and thus increase the efficiency of disaster management and relief operations. The generic design of the framework enables future extensions, thus enabling its exploitation across many application domains. The performance of the framework is evaluated in two areas: the capability of the access control mechanism to scale with increasing number of devices, and the capability of the semantic annotation process to increase in efficiency as more information is provided. The results demonstrate that the proposed framework is fit for purpose.