This thesis investigates the various techniques to achieve large time constants and the ultimate limitations therein. A novel circuit technique for the realization of large time constants for high pass corners in switched-capacitor filters is also proposed and compared with existing techniques. The switched-capacitor technique is insensitive to parasitic capacitances and is area efficient and it requires only two clock phases. The circuit is used to build a typical switched-capacitor front end with a gain of 10. The low pass corner is fixed at 200 Hz. The high pass corner is varied from 0.159Hz to 4 Hz and various performance parameters, such as power consumption, silicon area etc., are compared with conventional techniques and the advantages and disadvantages of each technique are demonstrated. The front-ends are fully differential and are chopper stabilized to protect against DC offsets and 1/f noise. The front-end is implemented in AMI0.6um technology with a supply voltage of 1.6V and all transistors operate in weak inversion with currents in the range of tens of nano-amperes.

This thesis investigates the various techniques to achieve large time constants and the ultimate limitations therein. A novel circuit technique for the realization of large time constants for high pass corners in switched-capacitor filters is also proposed and compared with existing techniques. The switched-capacitor technique is insensitive to parasitic capacitances and is area efficient and it requires only two clock phases. The circuit is used to build a typical switched-capacitor front end with a gain of 10. The low pass corner is fixed at 200 Hz. The high pass corner is varied from 0.159Hz to 4 Hz and various performance parameters, such as power consumption, silicon area etc., are compared with conventional techniques and the advantages and disadvantages of each technique are demonstrated. The front-ends are fully differential and are chopper stabilized to protect against DC offsets and 1/f noise. The front-end is implemented in AMI0.6um technology with a supply voltage of 1.6V and all transistors operate in weak inversion with currents in the range of tens of nano-amperes.

Abstract: This thesis is concerned with the acquisition of body signals using a sampling system. A typical application is the recording of the electrocardiogram (ECG). It is proposed to sample the input signal at different rates, depending on the momentary signal content. If the input signal has large voltage variation, it is sampled at a high rate. During periods of small variation, the signal is sampled at a lower frequency to save both memory and power. An analog controller to control the clock rate is proposed and implemented. The analog controller decides the sample frequency (high rate or low rate) depending on the input signal. The analysis of the proposed system is presented in this thesis. Furthermore, a working prototype is implemented using discrete components on a PCB. The measured results show a significant reduction in the average sample frequency and data rate of 50% and 35%, respectively. Finally, the critical analog circuit blocks of the system suitable for integration on chip are proposed and implemented in a 0.35£gm CMOS process. Measured results are reported to confirm the functionality of the blocks.