Power disspiation is a growing concern in VLSI circuits. In this work we model the data dependence of power dissipation by learning an input model which we use for estimation of both switching activity and crosstalk for every node in the circuit. We use Bayesian networks to effectively model the spatio-temporal dependence in the inputs and we use the probabilistic graphical model to learn the structure of the dependency in the inputs. The learned structure is representative of the input model. Since we learn a causal model, we can use a larger number of independencies which guarantees a minimal structure. The Bayesian network is converted into a moral graph, which is then triangulated. The junction tree is formed with its nodes representing the cliques. Then we use logic sampling on the junction tree and the sample required is really low. Experimental results with ISCAS '85 benchmark circuits show that we have achieved a very high compaction ratio with average error less than 2%. As HSPICE was used the results are the most accurate in terms of delay consideration. The results can further be used to predict the crosstalk between two neighboring nodes. This prediction helps in designing the circuit to avoid these problems.