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Design, Analysis and Implementation of Multiphase Synchronous Buck DC-DC Converter for Transportable ProcessorNguyen, Huy 13 May 2004 (has links)
As laptop mobile users expect more application features and long battery life, the processor current has to increase to response the demanding while the voltage has to decease to save the power loss. Therefore, it is necessary for a system designer to improve the efficiency of the voltage regulator converter (VRC) for the processor. Laptop processor architecture is more complicated than desktop because of different mode operations and their transitions. The laptop processor runs at different voltage levels for each operation mode to save the battery life. Therefore, the VRC needs to supply the correct and stable voltage to the processor. In this thesis, an analysis of power loss is derived to estimate the efficiency and switching frequency, three widely current sensing methods are discussed, two methods to compensate for the thermal resistance in loss less current sense methods are proposed, the tolerance of load line base on the component's tolerance in the converter is analyzed, the equation to estimate the output capacitance is derived, and the small signal analysis of multiphase synchronous buck converter with the droop current loop is derived.
A hardware prototype was implemented base on 4-phase synchronous buck topology to provide high efficiency and lower cost solution. The results of load line meets the Intel specification in different modes of operation, provides the best transient responses, and meets the specification during the load transient. The control loop lab measurement is also matched with the analysis and simulation. / Master of Science
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Low impedance characterisation and modeling of high power LDMOS devicesMalan, Pieter Jacob De Villiers 12 1900 (has links)
Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / In RF power transistor characterisation, the designer is confronted with low impedance
measurements (typically from 1 Ohm to 12 Ohm). These transistors are contained in
metal-ceramic packages of which the lead widths vary with power capability. This thesis
presents a high-quality fixture design with low impedance TRL calibration standards for
characterisation of an LDMOS transistor. Pre-matching networks are used to transform
to the low impedance environment. Since these pre-matching networks are independent
of the termination impedance, the low impedance port can always be designed to comply
with the same dimension as the device which is being measured.
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