This research aims at the development of a RF mass production load board for 4 bands cellular phone (850 MHz GSM-USA, 900 MHz GSM, 1.8 GHz DCS and 1.9 GHz PCS). To construct a strong theoretical foundation, the characteristics of key components such as relays, balun, cables, vias, micro strip line on the load board and the RF rules for PCB layout are extensively studied. An experimental load board is also specially designed to study the characteristics of RF printed circuit board. In this experimental load board, different materials (FR4 and Rogers) and transmission lines (microstrip lines and differential lines) are specially made and measured. After studying this experimental load board, we co-work with the RF load board supplier KeyStone to do the simulation as the preparation of production load board. In this simulation, the actual layout (Gerber file) of critical path together with the socket is checked for the resonance frequency. The production load board is manufactured in FR4 and debugged in the off-line debugging station before a correlation process in the ATE (automatic test equipment). Fine tune of 4 bands matching circuit is done by changing the value and/or the position of component on the matching circuit with VNA. After the fine tune, 70 good devices were tested twice on the same u-Flex tester with the developed load board and the one sent from test center in Europe (reference loadboard). The test results are processed by statistics tool ¡§Data Power¡¨ to calculate the mean value, variance, Cpk (biased process capability), R&R (Repeatability and Reproducibility), etc. The statistics results show the performance of the developed RF load board and the one from the test center in Europe is compatible and can be released for mass production. From this research, design flow of RF loadboard, highly relies on simulation to guarantee the performance of RF loadboard instead of basing on experience and/or trial and error, has been built up

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.