A bluff structure placed in a flowing fluid, may be subjected to vortex-induced vibrations (VIV). For a flat plate with only rotational degree of freedom, the VIV is rotational oscillation. Based on the experimental investigation, vortex-induced oscillation of the plate is studied. The Strouhal number is measured from the stationary plate in a low speed steady wind tunnel. A set of vibration tests are conducted to investigate the relationships between shedding frequency and vibration frequency. “lock-in” phenomena is observed with and without large amplitude. An empiricalanalytical model via introducing a nonlinear van der Pol oscillator is developed. This thesis investigates the “lock-in” phenomena of a flat plate in pitch oscillation. Results from wind tunnel experiments on a flat plate indicate the “lock-in” is frequency “lock-in”, resonance which appears large response amplitude occurs in the “lock-in” regime and may be influenced by “lock-in” phenomena.

Basically, to evaluate the operational performances of online auction is according to seller¡¦s transaction and investment in the auction website. Thus, how to maintain good relationship with the existing seller switching and attract new seller is the most attention and major care for auction service provider. However, there were few prior researches focused on the topic of online auction switching and examined from real case. In this study, we tried to develop a measuring model and explore the factors that relate to auction seller¡¦s switching. In July 2006, Yahoo! Kimo auction, the largest auction website in Taiwan, announced a new fee scheme which would charge 3 percent transaction handling fee on its sellers from Aug. 10. Many users expressed objection to the new charge scheme. During the same period, Ruten, a new joint venture auction website that combined eBay and Taiwanese portal operator PChome is nearly ready and makes some responding strategic approaches to attract new user. Many sellers of Yahoo! Kimo auction thought to switch auction provider. Base on the background, the study aim to explore auction seller¡¦s switching behavior through switching costs, including procedure costs, financial costs, and relational costs. Moreover, we examined how website quality, fee, anti-lock-in, and anti-switching affect switching intention and behavior. A total of 292 usable questionnaires were gathered through online surveys from auction discussion board and BBS. The data were analyzed by partial least squares (PLS) to test the hypotheses. We find that switching costs, website quality, fee have negative effect on seller¡¦s switching intention. Anti-lock-in and anti-switching have moderating effect in the model. According to the finding, we provide useful guidance for auction seller and auction service provider.

¡@¡@The first topic of this thesis is a high-speed digital clock generator circuit is presented to provide negative delays in order to avoid a multi-locking hazard. The negative delay also results in small power consumption and shorter access time if the proposed circuit is used in the clock generator circuit of memory devices. Meanwhile, an accurately locked clock signal is also provided. The locked clock signal can be as high as 1.0 GHz at the presence of a random noise with 10% of power supply voltage when the design is implemented by TSMC (Taiwan Semiconductor Manufacturing Company) 0.35um CMOS 1P4M technol- ogy. ¡@¡@The second topic of this thesis is an 1-to-4 joystick enhanced interface which can be attached to SONY PS2 (playstation 2) is developed. The enhanced interface can allow 4 persons to play simultaneously through one port at the original game console. A total of 8 players can be supported when two of the interfaces hook up with both joystick ports of the console. The multiple player entertainment effect can be drastically enhanced by the usage of such an interface.

This thesis proposes a novel technique using a phase-lock loop (PLL) style phase control loop to achieve retrodirective phased array antenna steering. This novel approach introduces the concept of phase scaling and frequency translation. It releases the retrodirective transmit-receive frequency ratio from integer constraints and avoids steering approximation errors. The concept was developed to achieve automatic and precise beam steering for the solar power satellite (SPS). The testing was performed using a transceiver converting a pair of received 2.9 GHz signals down to 10 MHz, and up converting two 10 MHz signals to 5.8 GHz. Phase scaling and conjugation was performed at the 10 MHz IF using linear XOR phase detectors and a PLL loop to synthesize a 10 MHz signal with conjugate phase. A phase control loop design is presented using PLL design theory achieving a full 2π steering range. The concept of retrodirective beam steering is also presented in detail. Operational theory and techniques of the proposed method are presented. The prototype circuit is built and the fabrication details are presented. Measured performance is presented along with measurement techniques. Pilot phase detectors and PCL achieve good linearity as required. The achieved performance is benchmarked with standards derived from likely performance requirements of the SPS and beam steering of small versus large arrays are considered.

Many entrepreneurial research studies underline implicitly the positive evidence of a connection between the economic success and networks. However, any social relationship which an entrepreneur maintains does not necessarily have positive effects and consequently does not represent a capital to the new established organization. Dysfunctional effects result from the circumstance that the different actors have different, sometimes contrary requirements on networks. The aim of our article is to explore dilemmatic constellations within networks and to enable entrepreneurial founders or consultants to face the related challenges.

Abstract: Instead of assuming that sixteenth-century poetry is a form of transcendence, and instead of defining poetry as an expression of inner life or character, this dissertation argues that there are ways to interpret poetry as a tool that helped sixteenth-century subjects understand and process embodied experience. How do we know that sixteenth-century poetry was a function of the material world and the body? The evidence is in the word selections, themes, and tropes created by poets themselves. By closely examining their writings, we can trace the negotiations between sixteenth-century poetic traditions, senses, and the material world. I explore these negotiations through three sixteenth-century poets whose works may be considered paradigmatic of the larger cultural movements that shaped their world: Sir Thomas Wyatt, the diplomat and courtier-poet in the reign of Henry VIII; Anne Vaughan Lock, a Marian exile who translated Calvin and published devotional poetry at the beginning of the reign of Elizabeth I; and William Shakespeare, whose sonnet sequence published in 1609 responded to Elizabethan cultural arts at a time of energy and change. The three poets engaged in this project are distinct in class, gender, and history, and thus, each chapter is a case study that surveys embodiment in a unique context. But the reason the three poets are viewed together (and the tie that binds them) is that they all wrote serial poems, or verse sequences. When compared across the project, important connections emerge about the cognitive power of serial poems. I argue that verse sequences are dexterous as well as able to perform cognitive "heavy lifting." Whether it was Vaughan Lock and Wyatt who dilated scriptural exemplars and carved space for emerging evangelical ideas, or Shakespeare, who much more clearly wrote inventive verse, sixteenth-century writers used the sequence to test new possibilities and integrate prior knowledge. In this diachronic reading of poetic embodiments, we can begin to see verse sequences as a technology that merges compelling perceptual observation with high abstraction, and that allows for opposing ideas to take place across the text, resolving rigid binaries and synthesizing opposites. Although my project attempts to view the poets together, each chapter provides evidence of significant differences across sixteenth-century poets. Although Wyatt and Vaughan Lock both utilized serial poems to test evangelical beliefs regarding conscience and penitence, they signal opposing impulses when it comes to gendered power. Moreover, Shakespeare's sonnets are more ostensibly amatory than religious in their overall intent. Shakespeare's metaliterary discourses, moreover, mobilized the serial format as an even more reflexive form. The project may be a skeletal map of the space between the evangelical procedures of conscience (which were themselves very reflexive) and Shakespearean procedures of mind. By comparing these differences, we may cast light on the ways in which psalm paraphrase (as a mode and a sequential format) influenced English amatory verse sequences. The dissertation works to address unstudied connections between diverse poets from the period of Henry VIII through the early reign of James I. But the dissertation also forges new routes in Renaissance studies, by proposing directions and methods for studying literary embodiment. I believe that sixteenth-century embodiment is best viewed through the lens of religious history and print technology. Moreover, I argue that the study of sixteenth-century embodiment should also incorporate contemporary historical ideas about the mind. By engaging both New Historicism and the discourse of embodied cognition from neuroscience, finally, the project creates a comparative view of cognition, translating between empirical methods and historicist techniques in English studies. / text

Nuclear magnetic resonance (NMR) spectroscopy and magnetic resonance imaging (MRI) are techniques widely utilized by many scientific fields, but their applications are often limited by short spin relaxation times and low sensitivity. This thesis explores two novel forms of NMR addressing these issues: nuclear spin singlet states for extending spin polarization lifetime and nitrogen-vacancy centers for sensing small samples. / Chemistry and Chemical Biology

Ο κύριος στόχος της διατριβής είναι η σχεδίαση των κύριων κυκλωμάτων ενός τηλεπικοινωνιακού συστήματος υπέρ–ευρείας ζώνης (UWB). Συγκεκριμένα, σχεδιάζονται σε τεχνολογία CMOS 90nm και αναπτύσσονται τα πλέον κρίσιμα κυκλώματα του PLL του FM-UWB πομπού με βάση ένα σύστημα FM-UWB, το οποίο στηρίζεται στη διπλή διαμόρφωση FM ευρείας ζώνης (double wideband FM modulation). Αυτά είναι το VCO, η αντλία φορτίου, ο διαιρέτης συχνότητας, και η γεννήτρια τάσης αναφοράς. Επιπλέον σχεδιάζονται ο δέκτης ο οποίος περιλαμβάνει τον προενισχυτή και τον αποδιαμορφωτή FM, δύο αρμονικοί ταλαντωτές ελεγχόμενοι από τάση για το υποσύστημα του πομπού σε τεχνολογία RF CMOS 65nm και ένας ταλαντωτής ελεγχόμενος από τάση τύπου δακτυλίου. Συνεπώς, στα πλαίσια της διατριβής αυτής σχεδιάζεται ολόκληρο το σύστημα πομπού και το σύστημα δέκτη (front-end) ώστε να αναδειχθούν οι δυνατότητες ολοκλήρωσης και τα πλεονεκτήματα της υλοποίησης ενός συστήματος FM-UWB σε πρόσφατες τεχνολογίες όπως η CMOS των 90nm και 65nm σε αντιδιαστολή με διπολικές τεχνολογίες. Με βάση τις λεπτομερείς προδιαγραφές που εξήχθησαν για τα υποσυστήματα και κυκλώματα του πομποδέκτη επιλέχτηκε η αρχιτεκτονική και σχεδιάστηκαν τα επιμέρους κυκλώματα στη ζώνη συχνοτήτων 3.1-5GHz. Για τη σχεδίαση χρησιμοποιήθηκαν το εργαλείο σχεδίασης «Cadence 5.1.41» και ο εξομοιωτής «Spectre». Για τη φυσική σχεδίαση έγινε χρήση του εργαλείων «Virtuoso XL» και «Assura». Ο πομπός αποτελείται από ένα γραμμικό VCO μεγάλου εύρους ζώνης (2.1GHz-5GHz) του οποίου η κεντρική συχνότητα ρυθμίζεται από ένα βρόχο κλειδωμένης φάσης (PLL) όταν δεν γίνεται μετάδοση δεδομένων. Στην ουσία πρόκειται για ένα PLL ο βρόχος του οποίου διακόπτεται όταν πραγματοποιείται εκπομπή πληροφορίας μέσω της διπλής διαμόρφωσης FM ενώ παραμένει κλειστός κατά τη ρύθμιση της κεντρικής συχνότητας του VCO (calibration). Το πιο κρίσιμο κύκλωμα του πομπού είναι το FM-UWB VCO. Για την ολοκλήρωση όμως του πομπού απαιτείται η σχεδίαση των υπόλοιπων κυκλωμάτων του βρόχου όπως είναι η αντλία φορτίου, ο διαιρέτης συχνότητας του βρόχου και ο ανιχνευτής φάσης-συχνότητας. Η τροφοδοσία του πομπού FM-UWB επιλέχτηκε να είναι ίση με 1V προκειμένου να ενισχυθεί η ανταγωνιστικότητα του με άλλα παρόμοια σύγχρονα συστήματα της βιβλιογραφίας. Με αρχικό στόχο την πόλωση των αναλογικών κυκλωμάτων του πομπού FM-UWB (αντλία φορτίου, διαιρέτης συχνότητας του PLL) αναπτύχθηκε μια γεννήτρια συνεχούς τάσης σε τροφοδοσία κάτω του 1V. Ο δέκτης αποτελείται από ένα συντονιζόμενο προενισχυτή και έναν αποδιαμορφωτή συχνότητας FM που σχεδιάζονται στη κεντρική συχνότητα των 4GHz με εύρος ζώνης μεγαλύτερου από 500MHz. Ο προτεινόμενος ταλαντωτής ελεγχόμενος από τάση (VCO), χαρακτηρίζεται από μεγάλο εύρος ζώνης συχνοτήτων ταλάντωσης, χαμηλή κατανάλωση και είναι κατάλληλος για iii εφαρμογές FM-UWB. Ο ταλαντωτής αυτός αποτελεί το βασικό δομικό στοιχείο ενός FM-UWB πομπού. Σχεδιάστηκε στην τεχνολογία υλοποίησης TSMC 90-nm digital CMOS, σε τάση τροφοδοσίας 1V και χαρακτηρίζεται από γραμμικό εύρος ζώνης συχνοτήτων ταλάντωσης μεταξύ 2.1GHz και 5GHz, διαφορική ισχύ εξόδου ίση με -7.83dBm  0.78dB και χαμηλή κατανάλωση ισχύος 8.26mW, συμπεριλαμβανομένης και της κατανάλωσης ισχύος των απομονωτών τάσης εξόδου (output buffers), στη μέγιστη συχνότητα ταλάντωσης. Επιπροσθέτως, έχει βελτιστοποιηθεί ως προς το λόγο εύρους ζώνης συχνοτήτων ταλάντωσης προς την κατανάλωση ισχύος TR/PDC. Η πρώτη βελτιστοποίηση έδωσε τιμή 9.95dB και η τελική έδωσε 11.97dB. Η επιθυμητή ζώνη συχνοτήτων ταλάντωσης μεταξύ 3.1GHz και 5GHz για εφαρμογές FM-UWB υπερκαλύπτεται για ολόκληρο το εύρος θερμοκρασιών που συναντάται στη βιομηχανία (από -40 oC έως 125 oC). Το εύρος συχνοτήτων ταλάντωσης βελτιώθηκε στο 130.15% (από 81.69%) και το FOM αυξήθηκε σε 143.08 (από 137.03). Επιπλέον, στη διατριβή αυτή παρουσιάζεται η σχεδίαση προγραμματιζόμενων, αντλιών φορτίου μεγάλης ακριβείας σε τάση τροφοδοσίας 1V. Τρείς συνολικά τοπολογίες μελετώνται με βασικό στόχο το καλύτερο δυνατό ταίριασμα των ρευμάτων εξόδου καθώς και τη μείωση των απότομων παρυφών ρεύματος στην έξοδο για μεγάλο εύρος τάσης εξόδου ώστε να επιτυγχάνεται αποδοτική χρήση της διαθέσιμης τάσης τροφοδοσίας (ΔVout/Vdd). Οι αντλίες φορτίου Ι, ΙΙ και ΙΙΙ χαρακτηρίζονται από μη ταίριασμα DC ρευμάτων εξόδου ίσο με 1%, 1.846% και 8% αντίστοιχα. Επιτυγχάνεται μεγαλύτερη μείωση των απότομων παρυφών ρεύματος στην έξοδο της αντλίας φορτίου ΙΙΙ σε σχέση με τις αντλίες φορτίου Ι και ΙΙ και μεγαλύτερη ταχύτητα λειτουργίας εις βάρος όμως της κατανάλωσης ισχύος. Ένα ολοκληρωμένο κύκλωμα γεννήτριας τάσης αναφοράς (Voltage reference) σχεδιάζεται επίσης, ώστε να χρησιμοποιηθεί ως κύκλωμα πόλωσης χαμηλής τροφοδοσίας κάτω του 1V ολοκληρωμένων κυκλωμάτων γενικού σκοπού. Η συνολική απόλυτη μεταβολή της τάσης αναφοράς εξόδου ως προς την μεταβολή των παραμέτρων της τεχνολογίας υλοποίησης και τις μεταβολές της τάσης τροφοδοσίας σε ευρεία κλίμακα θερμοκρασίας από -360C και 1250C ισούται με +/-3.3%. Η συνολική κατανάλωση ισχύος ισούται με 208uW. Παρουσιάζεται ακόμη η σχεδίαση ενός υποσυστήματος (front-end) δέκτη FM-UWB χαμηλού ρυθμού μετάδοσης δεδομένων (LDR, Low Data Rate), 50Kbps και μικρής εμβέλειας (<10m) με εύρος ζώνης μεγαλύτερο από 500MHz στην κεντρική συχνότητα των 4GHz. Δίνεται αναλυτικά η σχεδίαση της προτεινόμενης τοπολογίας για τον δέκτη FM-UWB στην τεχνολογία RF CMOS 65 nm ώστε να ικανοποιούνται οι προδιαγραφές του συστήματος που εξήχθησαν κατόπιν ανάλυσης. Τα αποτελέσματα του τελικού σχεδιασμού αποδεικνύουν ότι η συγκεκριμένη τεχνολογία, όταν συνδυάζεται με προσεκτικές επιλογές στη σχεδίαση μπορεί να πετύχει επιδόσεις συγκρίσιμες με τεχνολογίες SiGe BiCMOS που έχουν ενδογενή πλεονεκτήματα λόγω των ειδικών χαρακτηριστικών τους. iv Ο δέκτης FM-UWB αποτελείται από έναν προενισχυτή και ένα αποδιαμορφωτή συχνότητας FM-UWB. Η τεχνολογία υλοποίησης επιλέχτηκε να είναι η CMOS IBM των 65nm. Το συνολικό ρεύμα που απαιτείται για τη λειτουργία του πυρήνα του δέκτη FM-UWB είναι 8.093mA σε τροφοδοσία 1.8V και η ευαισθησία του δέκτη ισούται με -75.78dBm για λόγο σήματος προς θόρυβο SNRsub ίσο με 13.539dB. Συνεπώς, ικανοποιούνται πλήρως οι προδιαγραφές οι οποίες τέθηκαν ύστερα από τη μελέτη του τηλεπικοινωνιακού συστήματος FM-UWB. Η ευαισθησία του δέκτη αποδεικνύεται ότι μπορεί να αυξηθεί σε -82.95dBm για SNRsub ίσο με 13.539dB εάν προστεθεί ένα ακόμα στάδιο ενίσχυσης στο στάδιο καθυστέρησης του αποδιαμορφωτή FM-UWB με επιβάρυνση επιπλέον 8.033mW. Σχεδιάζεται επιπροσθέτως ένας αρμονικός ταλαντωτής για τον πομπό στα 65 nm ώστε να αναδειχθούν τα πιθανά οφέλη που μπορούν να προκύψουν όταν θυσιάζεται εύρος ζώνης και επιφάνεια ολοκλήρωσης εις όφελος της κατανάλωσης και των επιδόσεων του θορύβου φάσης. Για το συντονισμό αυτού του αρμονικού ταλαντωτή γίνεται χρήση μιας «hyperabrupt varactor» ώστε να επιτευχθεί εύρος ζώνης συχνοτήτων ταλάντωσης με καλή γραμμικότητα σε σύγκριση με αρμονικούς ταλαντωτές με απλή «varactor». Η συνολική κατανάλωση του πομπού FM-UWB ισούται με 5.11mW (συμπεριλαμβανομένης και της κατανάλωσης ισχύος του ενισχυτή εξόδου), ενώ το συνολικό γραμμικό εύρος ζώνης συχνοτήτων και το FOM του προτεινόμενου LC VCO ισούνται με 808ΜΗz και -173.679dB αντίστοιχα. Η ισχύς εξόδου του πομπού είναι μεγαλύτερη από -12dBm στη συχνότητα 4.14GHz και μεταβάλλεται λιγότερο από 0.5dB σε ολόκληρο το εύρος συχνοτήτων ταλάντωσης. Η καλή λειτουργία του εξασφαλίζεται στο εύρος θερμοκρασίας μεταξύ -40 0C και 1200C με θόρυβο φάσης στα 4.14GHz καλύτερο από -100dBc/Hz σε απόκλιση συχνότητας από τον φορέα 1ΜΗz. Στη συνέχεια, η ιδέα της επαναχρησιμοποίησης ρεύματος εφαρμόζεται στον παραπάνω αρμονικό ταλαντωτή-FM-UWB πομπό στα 65nm ούτως ώστε ο απομονωτής εξόδου να τοποθετείται πάνω από τον πυρήνα του LC VCO. Αυτό οδήγησε στη μείωση της αρχικής κατανάλωσης ισχύος (έως και 73.63%) ενώ διατηρήθηκαν τα παραπάνω χαρακτηριστικά του. Τέλος, σχεδιάστηκε ένα VCO τύπου δακτυλίου σε τροφοδοσία 1.8V, στα 65 nm. Καλύπτει τη ζώνη συχνοτήτων από 3.1GHz έως 5GHz με θόρυβο φάσης καλύτερο από -83dBc/Hz σε απόκλιση συχνότητας από τον φορέα ίση με 1MHz, με εύρος ζώνης διαμόρφωσης ίσο με 1MHz, παρέχοντας στην έξοδο του ισχύ μεγαλύτερη από -12dBm ενώ καταναλώνει 3.63mW. / The main purpose of this thesis is the design of the critical circuits of an Ultra Wideband (UWB) communication system. More specifically, circuits were designed for an FM-UWB system which relies on a double constant envelope FM modulation scheme. The most critical circuits of the transmitter PLL are designed in a 90nm CMOS process. These are the VCO, the loop divider, the charge pump and the voltage reference. In addition, the FM-UWB receiver front-end is designed in a 65nm RF CMOS process which includes an LNA/Preamplifier and a FM-UWB demodulator. Two harmonic LC-VCOs are also designed and one ring current-starved VCO to function as FM-UWB modulators in the transmitter path. Consequently, in this thesis the full transceiver front-end is designed in order to demonstrate the potential of its integration and the advantages of the implementation of an FM-UWB system in recent CMOS technologies such as those of 90nm and 65nm in comparison with bipolar implementations. Based on system study, the front-end circuits’ specifications were derived, the appropriate front-end architecture was selected and the front-end circuits were designed in the band of 3.1-5GHz. For the circuit design the tools of Cadence 5.1.41 and the Spectre RF Simulator were used. For the circuits layout designs the tools of Virtuoso XL and Assura were used. The transmitter consists of a linear VCO with wide tuning range (2.1GHz-5GHz) of which the central frequency is calibrated by a Phase Locked Loop when data transmission is ceased. The loop remains open when data transmission has to take place and stays closed when the VCO central frequency has to be calibrated. The most important block of the transmitter is the FM-UWB VCO. For the completion of the FM-UWB transmitter the design of other blocks such as the charge pump, the loop divider, the phase frequency detector and the voltage reference generator design is important as well. The supply voltage of 1V was selected for the FM-UWB transmitter in order to become competitive against other recent published implementations. Targeting at the biasing of the loop divider and the charge pump at the low supply voltage of 1V, a Sub-1V voltage reference generator was designed. The receiver consists of a wideband LNA/Preamplifier and a wideband FM demodulator with a center frequency at 4GHz and a useful bandwidth higher than 500MHz. Targeting at the implementation of wide frequency range (3.1-5GHz), the main purpose was the design of a linear, inductorless, low power (less than 10mW), low area, low supply voltage controlled oscillator with a phase noise better than -70dBc/Hz at 1MHz offset and small output power variation over the entire tuning range. The proposed FM-UWB VCO was designed in a 90-nm standard digital CMOS process at a supply voltage of 1V and a relatively linear tuning range is achieved between the frequencies of 2.1GHz and 5GHz, a differential vi output power of -7.83dBm 0.78dB and a low power consumption of 8.26mW when the output buffers power consumption is included at the maximum frequency of oscillation. The proposed FM-UWB VCO was optimized for the ratio of tuning range over the power consumption TR/PDC. The first optimization yields TR/PDC equal to 9.95dB and the final optimization yields TR/PDC equal to 11.974dB. The desired oscillation frequency band between 3.1GHz and 5GHz for FM-UWB applications is fully covered for the entire industrial temperature range of -40 0C to 125 0C. The tuning range of the improved VCO equals 130.15% (from 81.69%) whereas the improved VCO FOM was increased to 143.08 (from 137.03). Afterwards, programmable charge pumps with high accuracy were designed operating at the supply voltage of 1V. These charge pumps can be used in the PLL of the FM-UWB transmitter or in PLLs used for different telecommunication applications. Three in total charge pumps were designed aiming at a very good DC mismatch between the output source and sink currents, the reduction of the output source and sink current glitches for the maximum possible output voltage range. Charge pumps I, II and III achieve DC mismatch of 1%, 1.846% and 8% respectively. Charge pump III achieve lower output current glitches and higher speed of operation when compared to charge pumps I and II at the expense of higher power consumption. Furthermore, an integrated sub-1V voltage reference generator is presented. It is designed in standard 90-nm CMOS technology. The output reference voltage achieves a total absolute variation of ±3.3% over all process and supply voltage variations. The total power consumption equals 208μW. The proposed low data rate (50Kbps), short range (<10m), FM-UWB receiver front-end is designed in 65nm RF CMOS technology at a supply voltage of 1.8V with a useful bandwidth higher than 500MHz at the center frequency of 4GHz and the current reuse technique is applied aiming at the reduction of the overall power consumption around 14mW. It consists of a wideband preamplifier and a wideband FM demodulator. Final results show that CMOS technology at 65nm when it is combined with careful circuit design and specific circuit topologies can achieve comparable performance to SiGe BiCMOS technologies which have inherent advantages due to their special characteristics. The total bias current of the FM-UWB receiver core is only 8.093mA at a supply voltage of 1.8V and the receiver sensitivity equals -75.78dBm at a signal to noise ratio, SNRsub equal to 13.539dB. The receiver sensitivity can be improved to -82.95dBm at a signal to noise ratio, SNRsub equal to 13.539dB when an additional amplification stage is included in the delay element of the FM-UWB demodulator at the price of extra 8.033mW. Moreover, the design of an FM-UWB LC VCO in the 65nm RF CMOS technology is proposed as the main block of an FM-UWB transmitter. A hyperabrupt varactor is used in the vii tank of the proposed LC VCO in order to achieve linear tuning range. The total power consumption of the proposed LC FM-UWB VCO is 5.11mW including the power consumption of the output buffers, the total linear frequency range and the figure of merit, FOM equal 808MHz and -173.679dB respectively. The suggested LC VCO output power level is higher -12dBm at the frequency of 4.14GHz and varies less than 0.5dB in the entire frequency range of operation. The operation of the suggested VCO is ensured for the entire industrial temperature range between -40 0C and 120 0C with a phase noise performance better than -100dBc/Hz at the frequency offset of 1MHz at 4.14GHz. The above described performance of the proposed FM-UWB LC VCO is improved in terms of power consumption by applying the current reuse technique for the LC VCO core and the output buffer. By stacking the LC VCO core with the output buffer the power consumption can be reduced by 73.63% in comparison with the previously described LC VCO whereas the other VCO characteristics remain the same apart from the output power level which is reduced. Furthermore, a linear, inductorless VCO is proposed. This VCO is designed in 65nm RF CMOS technology and is based on the current starved topology. The suggested VCO tuning is achieved by modulating the current of the VCO core linearly by a voltage to current converter. This VCO is suitable for the FM-UWB application since it covers the frequency range between 3.1GHz to 5GHz and it achieves a phase noise performance of better than -83dBc/Hz at 1MHz offset. The VCO buffer delivers to a 50 Ohm load output power of better than -12dBm. The total VCO power consumption equals 3.63mW (including the output buffer) at a supply voltage of 1.8V and the VCO maximum modulation bandwidth equals 1MHz. Finally, it should be noted that the design of LC harmonic VCOs based on the use of hyperabrupt varactor and the linear current starved VCO design which took place in the last period of this thesis shows our effort to improve the performance of our previous work in the area of VCO circuit design by taking into account the latest published achievements of the literature. In conclusion, in this thesis all of the main VCO topologies were studied and designed for the needs of an FM-UWB transmitter front-end.

French literary translators have traditionally translated in an ethnocentric fashion in such a way that the translated work did not seem translated. They tried to write their translations in the same way the author would have, had he been French. Readers of French translations seemed quite satisfied with that approach. Yet there are translators who do not feel comfortable with this ethnocentric approach. They have done a great deal of reflection on their work, and are introducing new ways of translating literature. One of these is Antoine Berman. We have dedicated the first half of our work to his theories and the second half to a possible application of these theories to a novel by Joyce Carol Oates, I Lock my Door upon Myself. This novel was translated in France by Marie-Lise Marliere and its French title is Un amour noir. We will quote examples from the translation where we feel we can apply Berman's theory of "distorting tendencies" and make practical suggestions of alternative French translations. Our conclusion leads us to explore ways to better serve the French readers of Joyce Carol Oates.

Existing atomic section interface proposals, thus far, have tended to only isolate transactions from each other. Less considered is the coordination of threads performing transactions with respect to one another. Synchronization of nested sections is typically relegated to outside of and among the top-level flattened sections. However existing models do not permit the composition of even simple synchronization constructs such as barriers. The proposed model integrates synchronization as a first-class construct in a truly nested atomic block implementation. The implementation is evaluated on quantitative benchmarks, with qualitative examples of the atomic section interface???s expressive power compared with conventional transactional memory implementations.